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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5

18-36 Freescale Semiconductor

18.4.2.3.4 eTPU Channel Data Transfer Request Overflow Status Register

(ETPU_CDTROSR)

Data transfer request overflow status from all channels are grouped in ETPU_CDTROSR. The bits are

mirrored by the channels’ status/control registers. For more information on channel status registers and

data transfer request overflow, refer to Section 18.4.2.4.3, “eTPU Channel n Status Control Register

(ETPU_CnSCR),” and the eTPU reference manual.

NOTE

The host must write 1 to clear a data transfer request overflow status bit.

18.4.2.3.5 eTPU Channel Interrupt Enable Register (ETPU_CIER)

The host interrupt enable bits for all 32 channels are grouped in ETPU_CIER. The bits are mirrored by the

channel configuration registers. For more information on channel configuration registers and interrupt

enable, refer to Section 18.4.2.4.2, “eTPU Channel n Configuration Register (ETPU_CnCR),” and the

eTPU reference manual.

0123456789101112131415

DTROS

W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c

Reset0000000000000000

Reg Addr eTPU A: BASE + 0x0_0230 / eTPU B: BASE + 0x0_0234

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

DTROS

W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c

Reset0000000000000000

Reg Addr eTPU A: BASE + 0x0_0230 / eTPU B: BASE + 0x0_0234

Figure 18-17. eTPU Channel Data Transfer Request Overflow

Status Register (ETPU_CDTROSR)

Table 18-19. ETPU_CDTROSR Field Descriptions

Bits Name Description

0–31 DTROSn Channel n data transfer request overflow status.

0 indicates that no data transfer request overflow occurred in the channel

1 indicates that a data transfer request overflow occurred in the channel.

To clear a status bit, the host must write 1 to it.

For details about data transfer request overflow, refer to the eTPU reference manual.

Freescale Semiconductor MPC5553 - Page 743