Freescale Semiconductor MPC5553 - Page 863

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
19-108 Freescale Semiconductor
Step Two: Configure the eDMA to handle data transfers between the command/result queues in RAM and
the CFIFOs/RFIFOs in the eQADC.
1. For transferring, set the source address of the eDMA TCDn to point to the start address of
command queue 1. Set the destination address of the eDMA to point to EQADC_CFPR1. Refer to
Section 19.3.2.4, “eQADC CFIFO Push Registers 0–5 (EQADC_CFPRn).”
2. For receiving, set the source address of the eDMA TCDn to point to EQADC_RFPR3. Refer to
Section 19.3.2.5, “eQADC Result FIFO Pop Registers 0–5 (EQADC_RFPRn).” Set the
destination address of the eDMA to point to the starting address of result queue 1.
Step Three: Configure the eQADC control registers.
3. Configure Section 19.3.2.7, “eQADC Interrupt and eDMA Control Registers 0–5
(EQADC_IDCRn).”
a) Set EOQIE1 to enable the End of Queue Interrupt request.
b) Set CFFS1 and RFDS3 to configure the eQADC to generate eDMA requests to push
commands into CFIFO1 and to pop result data from RFIF03.
c) Set CFINV1 to invalidate the contents of CFIFO1.
d) Set RFDE3 and CFFE1 to enable the eQADC to generate eDMA requests. Command
transfers from the RAM to the CFIFO1 will start immediately.
e) Set RFOIE3 to indicate if RFIFO3 overflows.
f) Set CFUIE1 to indicate if CFIFO1 underflows.
4. Configure MODE1 to continuous-scan rising edge external trigger mode in Section 19.3.2.6,
“eQADC CFIFO Control Registers 0–5 (EQADC_CFCRn).”
Step Four: Command transfer to ADCs and result data reception.
When an external rising edge event occurs for CFIFO1, the eQADC automatically will begin
transferring commands from CFIFO1 when it becomes the highest priority CFIFO trying to send
commands to ADC1. The received results will be placed in RFIFO3 and then moved to result
queue 1 by the eDMA.
CMDEOQ10 0 0010 0b0011 EOQ Message
1
Fields LST, TSR, FMT, and CHANNEL_NUMBER are not shown for clarity. See Section , “ Conversion Command
Message Format for On-Chip ADC Operation,” for details.
2
MESSAGE_TAG field is only defined for read configuration commands.
Table 19-57. Example of Command Queue Commands
1
01234567891
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
EOQ PAUSE RESERVED ABORT_ST EB (0b1) BN CAL
MESSAGE
TAG
ADC COMMAND
CFIFO Header ADC Command