GigaDevice Semiconductor GD32F3x0 - Page 3

GD32F3x0 User Manual
3
2.3.9. Option byte description ......................................................................................................... 47
2.3.10. Page erase/Program protection ............................................................................................ 48
2.3.11. Security protection ................................................................................................................ 49
2.4. Register definition.......................................................................................................... 50
2.4.1. Wait state register (FMC_WS) .............................................................................................. 50
2.4.2. Unlock key register (FMC_KEY) ........................................................................................... 50
2.4.3. Option byte unlock key register (FMC_OBKEY) ................................................................... 51
2.4.4. Status register (FMC_STAT) ................................................................................................. 51
2.4.5. Control register (FMC_CTL) ................................................................................................. 52
2.4.6. Address register (FMC_ADDR) ............................................................................................ 53
2.4.7. Option byte status register (FMC_OBSTAT) ......................................................................... 54
2.4.8. Write protection register (FMC_WP) ..................................................................................... 54
2.4.9. Wait state enable register (FMC_WSEN) ............................................................................. 55
2.4.10. Product ID register (FMC_PID)............................................................................................. 55
3. Power management unit (PMU) ............................................................................ 57
3.1. Overview ......................................................................................................................... 57
3.2. Characteristics ............................................................................................................... 57
3.3. Function overview.......................................................................................................... 57
3.3.1. Backup domain ..................................................................................................................... 58
3.3.2. V
DD
/ V
DDA
power domain ...................................................................................................... 59
3.3.3. 1.2V power domain ............................................................................................................... 61
3.3.4. Power saving modes ............................................................................................................ 61
3.4. Register definition.......................................................................................................... 65
3.4.1. Control register (PMU_CTL) ................................................................................................. 65
3.4.2. Control and status register (PMU_CS) ................................................................................. 67
4. Reset and clock unit (RCU) ................................................................................... 70
4.1. Reset control unit (RCTL) ............................................................................................. 70
4.1.1. Overview ............................................................................................................................... 70
4.1.2. Function overview ................................................................................................................. 70
4.2. Clock control unit (CCTL) ............................................................................................. 71
4.2.1. Overview ............................................................................................................................... 71
4.2.2. Characteristics ...................................................................................................................... 73
4.2.3. Function overview ................................................................................................................. 73
4.3. Register definition.......................................................................................................... 78
4.3.1. Control register0 (RCU_CTL0) ............................................................................................. 78
4.3.2. Configuration register 0 (RCU_CFG0) ................................................................................. 79
4.3.3. Interrupt register (RCU_INT) ................................................................................................ 83
4.3.4. APB2 reset register (RCU_APB2RST) ................................................................................. 86
4.3.5. APB1 reset register (RCU_APB1RST) ................................................................................. 87
4.3.6. AHB enable register (RCU_AHBEN) .................................................................................... 89