GigaDevice Semiconductor GD32F3x0 - Page 4

GD32F3x0 User Manual
4
4.3.7. APB2 enable register (RCU_APB2EN) ................................................................................ 91
4.3.8. APB1 enable register (RCU_APB1EN) ................................................................................ 92
4.3.9. Backup domain control register (RCU_BDCTL) ................................................................... 94
4.3.10. Reset source /clock register (RCU_RSTSCK) ..................................................................... 96
4.3.11. AHB reset register (RCU_AHBRST)..................................................................................... 97
4.3.12. Configuration register 1 (RCU_CFG1) ................................................................................. 99
4.3.13. Configuration register 2 (RCU_CFG2) ............................................................................... 100
4.3.14. Control register 1 (RCU_CTL1) .......................................................................................... 101
4.3.15. Additional clock control register (RCU_ADDCTL) .............................................................. 101
4.3.16. Additional clock interrupt register (RCU_ADDINT) ............................................................. 102
4.3.17. APB1 additional enable register (RCU_ADDAPB1EN) ...................................................... 103
4.3.18. APB1 additional reset register (RCU_ADDAPB1RST) ....................................................... 104
4.3.19. Voltage key register (RCU_VKEY) ..................................................................................... 104
4.3.20. Deep-sleep mode voltage register (RCU_DSV) ................................................................. 105
5. Clock trim controller (CTC) ................................................................................. 106
5.1. Overview ....................................................................................................................... 106
5.2. Characteristics ............................................................................................................. 106
5.3. Function overview........................................................................................................ 106
5.3.1. REF sync pulse generator .................................................................................................. 107
5.3.2. CTC trim counter................................................................................................................. 107
5.3.3. Frequency evaluation and automatically trim process........................................................ 108
5.3.4. Software program guide ..................................................................................................... 109
5.4. Register definition........................................................................................................ 110
5.4.1. Control register 0 (CTC_CTL0) ............................................................................................ 110
5.4.2. Control register 1 (CTC_CTL1) ............................................................................................ 111
5.4.3. Status register (CTC_STAT) ................................................................................................ 112
5.4.4. Interrupt clear register (CTC_INTC) .................................................................................... 114
6. Interrupt/event controller (EXTI) ......................................................................... 116
6.1. Overview ....................................................................................................................... 116
6.2. Characteristics ............................................................................................................. 116
6.3. Interrupts function overview ...................................................................................... 116
6.4. External interrupt and event (EXTI) block diagram.................................................. 119
6.5. External interrupt and Event function overview ...................................................... 119
6.6. Register definition........................................................................................................ 121
6.6.1. Interrupt enable register (EXTI_INTEN) ............................................................................. 121
6.6.2. Event enable register (EXTI_EVEN) .................................................................................. 121
6.6.3. Rising edge trigger enable register (EXTI_RTEN) ............................................................. 122
6.6.4. Falling edge trigger enable register (EXTI_FTEN) ............................................................. 122
6.6.5. Software interrupt event register (EXTI_SWIEV) ............................................................... 123