GD32F3x0 User Manual
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6.6.6. Pending register (EXTI_PD) ............................................................................................... 123
7. General-purpose and alternate-function I/Os (GPIO) ........................................ 125
7.1. Overview ....................................................................................................................... 125
7.2. Characteristics ............................................................................................................. 125
7.3. Function overview........................................................................................................ 125
7.3.1. GPIO pin configuration ....................................................................................................... 126
7.3.2. Alternate functions (AF) ...................................................................................................... 127
7.3.3. Additional functions ............................................................................................................. 127
7.3.4. Input configuration .............................................................................................................. 127
7.3.5. Output configuration ........................................................................................................... 128
7.3.6. Analog configuration ........................................................................................................... 128
7.3.7. Alternate function (AF) configuration .................................................................................. 129
7.3.8. GPIO locking function ......................................................................................................... 130
7.3.9. GPIO single cycle toggle function ....................................................................................... 130
7.3.10. GPIO very high speed drive capability ............................................................................... 130
7.4. Register definition........................................................................................................ 131
7.4.1. Port control register (GPIOx_CTL, x=A..D,F) ..................................................................... 131
7.4.2. Port output mode register (GPIOx_OMODE, x=A..D,F) ..................................................... 132
7.4.3. Port output speed register 0 (GPIOx_OSPD0, x=A..D,F) ................................................... 134
7.4.4. Port pull-up/down register (GPIOx_PUD, x=A..D,F) ........................................................... 136
7.4.5. Port input status register (GPIOx_ISTAT, x=A..D,F) ........................................................... 137
7.4.6. Port output control register (GPIOx_OCTL, x=A..D,F) ....................................................... 138
7.4.7. Port bit operate register (GPIOx_BOP, x=A..D,F)............................................................... 138
7.4.8. Port configuration lock register (GPIOx_LOCK, x=A,B) ..................................................... 139
7.4.9. Alternate function selected register 0 (GPIOx_AFSEL0, x=A,B,C) .................................... 140
7.4.10. Alternate function selected register 1 (GPIOx_AFSEL1, x=A,B,C) .................................... 141
7.4.11. Bit clear register (GPIOx_BC, x=A..D,F) ............................................................................ 142
7.4.12. Port bit toggle register (GPIOx_TG, x=A..D,F) ................................................................... 142
7.4.13. Port output speed register 1 (GPIOx_OSPD1, x=A..D,F) ................................................... 143
8. Cyclic redundancy checks management unit (CRC) ........................................ 144
8.1. Overview ....................................................................................................................... 144
8.2. Characteristics ............................................................................................................. 144
8.3. Function overview........................................................................................................ 145
8.4. Register definition........................................................................................................ 146
8.4.1. Data register (CRC_DATA) ................................................................................................. 146
8.4.2. Free data register (CRC_FDATA) ....................................................................................... 146
8.4.3. Control register (CRC_CTL) ............................................................................................... 147
8.4.4. Initialization data register (CRC_IDATA) ............................................................................. 147
8.4.5. Polynomial register (CRC_POLY) ....................................................................................... 148