GigaDevice Semiconductor GD32F3x0 - Page 6

GD32F3x0 User Manual
6
9. Direct memory access controller (DMA) ............................................................ 149
9.1. Overview ....................................................................................................................... 149
9.2. Characteristics ............................................................................................................. 149
9.3. Block diagram .............................................................................................................. 150
9.4. Function overview........................................................................................................ 150
9.4.1. DMA operation .................................................................................................................... 150
9.4.2. Peripheral handshake ......................................................................................................... 152
9.4.3. Arbitration ............................................................................................................................ 152
9.4.4. Address generation ............................................................................................................. 153
9.4.5. Circular mode...................................................................................................................... 153
9.4.6. Memory to memory mode ................................................................................................... 153
9.4.7. Channel configuration ......................................................................................................... 153
9.4.8. Interrupt ............................................................................................................................... 154
9.4.9. DMA request mapping ........................................................................................................ 155
9.5. Register definition........................................................................................................ 158
9.5.1. Interrupt flag register (DMA_INTF) ..................................................................................... 158
9.5.2. Interrupt flag clear register (DMA_INTC) ............................................................................ 158
9.5.3. Channel x control register (DMA_CHxCTL) ....................................................................... 159
9.5.4. Channel x counter register (DMA_CHxCNT) ...................................................................... 161
9.5.5. Channel x peripheral base address register (DMA_CHxPADDR) ...................................... 162
9.5.6. Channel x memory base address register (DMA_CHxMADDR) ........................................ 162
10. Debug (DBG) ..................................................................................................... 164
10.1. Overview .................................................................................................................... 164
10.2. Serial Wire Debug port overview ............................................................................ 164
10.2.1. Pin assignment ................................................................................................................... 164
10.2.2. JEDEC-106 ID code ........................................................................................................... 164
10.3. Debug hold function overview ................................................................................ 165
10.3.1. Debug support for power saving mode ............................................................................... 165
10.3.2. Debug support for TIMER, I2C, RTC, WWDGT and FWDGT ............................................ 165
10.4. Register definition .................................................................................................... 166
10.4.1. ID code register (DBG_ID) .................................................................................................. 166
10.4.2. Control register 0 (DBG_CTL0) .......................................................................................... 166
10.4.3. Control register 1 (DBG_CTL1) .......................................................................................... 168
11. Analog to digital converter (ADC) ................................................................... 170
11.1. Overview .................................................................................................................... 170
11.2. Characteristics .......................................................................................................... 170
11.3. Pins and internal signals ......................................................................................... 171
11.4. Function overview .................................................................................................... 172