GigaDevice Semiconductor GD32F3x0 - Page 7

GD32F3x0 User Manual
7
11.4.1. Foreground calibration function .......................................................................................... 172
11.4.2. Dual clock domain architecture ........................................................................................... 173
11.4.3. ADCON enable ................................................................................................................... 173
11.4.4. Routine sequence ............................................................................................................... 173
11.4.5. Operation modes ................................................................................................................ 173
11.4.6. Conversion result threshold monitor function ..................................................................... 176
11.4.7. Data storage mode ............................................................................................................. 176
11.4.8. Sample time configuration .................................................................................................. 177
11.4.9. External trigger configuration .............................................................................................. 178
11.4.10. DMA request ....................................................................................................................... 178
11.4.11. ADC internal channels ........................................................................................................ 178
11.4.12. ADC interrupts .................................................................................................................... 179
11.4.13. Programmable resolution (DRES) ...................................................................................... 179
11.4.14. On-chip hardware oversampling ......................................................................................... 180
11.5. Register definition .................................................................................................... 183
11.5.1. Status register (ADC_STAT) ............................................................................................... 183
11.5.2. Control register 0 (ADC_CTL0) .......................................................................................... 183
11.5.3. Control register 1 (ADC_CTL1) .......................................................................................... 185
11.5.4. Sampling time register 0 (ADC_SAMPT0) ......................................................................... 187
11.5.5. Sampling time register 1 (ADC_SAMPT1) ......................................................................... 187
11.5.6. Watchdog high threshold register (ADC_WDHT) ............................................................... 188
11.5.7. Watchdog low threshold register (ADC_WDLT) ................................................................. 189
11.5.8. Routine sequence register0(ADC_RSQ0) .......................................................................... 189
11.5.9. Routine sequence register1(ADC_RSQ1) .......................................................................... 190
11.5.10. Routine sequence register 2 (ADC_RSQ2) ........................................................................ 190
11.5.11. Routine data register (ADC_RDATA) .................................................................................. 191
11.5.12. Oversampling control register (ADC_OVSAMPCTL) ......................................................... 191
12. Digital-to-analog converter (DAC) ................................................................... 194
12.1. Overview .................................................................................................................... 194
12.2. Characteristic ............................................................................................................ 194
12.3. Function overview .................................................................................................... 195
12.3.1. DAC enable ......................................................................................................................... 195
12.3.2. DAC output buffer ............................................................................................................... 195
12.3.3. DAC data configuration ....................................................................................................... 195
12.3.4. DAC trigger ......................................................................................................................... 195
12.3.5. DAC workflow ..................................................................................................................... 196
12.3.6. DAC noise wave ................................................................................................................. 196
12.3.7. DAC output calculate .......................................................................................................... 197
12.3.8. DMA function....................................................................................................................... 197
12.4. Registers definition .................................................................................................. 198
12.4.1. Control register (DAC_CTL) ............................................................................................... 198