GigaDevice Semiconductor GD32F3x0 - Page 8

GD32F3x0 User Manual
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12.4.2. Software trigger register (DAC_SWT) ................................................................................ 199
12.4.3. DAC 12-bit right-aligned data holding register(DAC_R12DH) ............................................ 200
12.4.4. DAC 12-bit left-aligned data holding register(DAC_L12DH) .............................................. 200
12.4.5. DAC 8-bit right-aligned data holding register (DAC_R8DH) ............................................... 201
12.4.6. DAC data output register (DAC_DO) .................................................................................. 201
12.4.7. DAC Status register (DAC_STAT) ...................................................................................... 201
13. Comparator (CMP) ............................................................................................ 203
13.1. Overview .................................................................................................................... 203
13.2. Characteristic ............................................................................................................ 203
13.3. Function overview .................................................................................................... 203
13.3.1. CMP clock and reset ........................................................................................................... 204
13.3.2. CMP I/O configure .............................................................................................................. 204
13.3.3. CMP operating mode .......................................................................................................... 205
13.3.4. CMP hysteresis ................................................................................................................... 205
13.3.5. CMP register write protection ............................................................................................. 205
13.4. CMP registers ............................................................................................................ 206
13.4.1. Control/status register (CMP_CS) ...................................................................................... 206
14. Watchdog timer (WDGT) .................................................................................. 210
14.1. Free watchdog timer (FWDGT) ............................................................................... 210
14.1.1. Overview ............................................................................................................................. 210
14.1.2. Characteristics .................................................................................................................... 210
14.1.3. Function overview ............................................................................................................... 210
14.1.4. Register definition ............................................................................................................... 213
14.2. Window watchdog timer (WWDGT) ........................................................................ 217
14.2.1. Overview ............................................................................................................................. 217
14.2.2. Characteristics .................................................................................................................... 217
14.2.3. Function overview ............................................................................................................... 217
14.2.4. Register definition ............................................................................................................... 220
15. Real-time clock (RTC) ....................................................................................... 222
15.1. Overview .................................................................................................................... 222
15.2. Characteristics .......................................................................................................... 222
15.3. Function overview .................................................................................................... 223
15.3.1. Block diagram ..................................................................................................................... 223
15.3.2. Clock source and prescalers .............................................................................................. 223
15.3.3. Shadow registers introduction ............................................................................................ 224
15.3.4. Configurable and field maskable alarm .............................................................................. 224
15.3.5. RTC initialization and configuration .................................................................................... 225
15.3.6. Calendar reading ................................................................................................................ 226
15.3.7. Resetting the RTC .............................................................................................................. 227