GD32F3x0 User Manual
438
Single pulse mode
Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM
in TIMERx_CTL0. When you set SPM, the counter will be clear and stop when the next
update event.
Once the timer is set to operate in the single pulse mode, it is necessary to set the timer
enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter, then the CEN bit
keeps at a high state until the update event occurs or the CEN bit is written to 0 by software.
If the CEN bit is cleared to 0 using software, the counter will be stopped and its value held.
Timer debug mode
When the Cortex
®
-M4 halted, and the TIMERx_HOLD configuration bit in DBG_CTL0
register set to 1, the TIMERx counter stops.
To Next Page
Loading...
