GigaDevice Semiconductor GD32F3x0 - Page 466

GD32F3x0 User Manual
466
0: Oversampling by 16
1: Oversampling by 8
This bit must be kept cleared in LIN, IrDA and smartcard modes.
This bit field cannot be written when the USART is enabled (UEN=1).
14
AMIE
ADDR match interrupt enable
0: ADDR match interrupt is disabled.
1: ADDR match interrupt is enabled.
13
MEN
Mute mode enable
0: Mute mode disabled
1: Mute mode enabled
12
WL
Word length
0: 8 Data bits
1: 9 Data bits
This bit field cannot be written when the USART is enabled (UEN=1).
11
WM
Wakeup method in mute mode
0: Idle Line
1: Address match
This bit field cannot be written when the USART is enabled (UEN=1).
10
PCEN
Parity control enable
0: Parity control disabled
1: Parity control enabled
This bit field cannot be written when the USART is enabled (UEN=1).
9
PM
Parity mode
0: Even parity
1: Odd parity
This bit field cannot be written when the USART is enabled (UEN=1).
8
PERRIE
Parity error interrupt enable
0: Parity error interrupt is disabled.
1: An interrupt will occur whenever the PERR bit is set in USART_STAT.
7
TBEIE
Transmitter register empty interrupt enable
0: Interrupt is inhibited.
1: An interrupt will occur whenever the TBE bit is set in USART_STAT.
6
TCIE
Transmission complete interrupt enable
0: Transmission complete interrupt is disabled.
1: An interrupt will occur whenever the TC bit is set in USART_STAT.
5
RBNEIE
Read data buffer not empty interrupt and overrun error interrupt enable
0: Read data register not empty interrupt and overrun error interrupt disabled.
1: An interrupt will occur whenever the ORERR bit is set or the RBNE bit is set in