GigaDevice Semiconductor GD32F3x0 - Page 467

GD32F3x0 User Manual
467
USART_STAT.
4
IDLEIE
IDLE line detected interrupt enable
0: IDLE line detected interrupt disabled.
1: An interrupt will occur whenever the IDLEF bit is set in USART_STAT.
3
TEN
Transmitter enable
0: Transmitter is disabled.
1: Transmitter is enabled.
2
REN
Receiver enable
0: Receiver is disabled.
1: Receiver is enabled and begins searching for a start bit.
1
UESM
USART enable in Deep-sleep mode
0: USART not able to wake up the MCU from deep-sleep mode.
1: USART able to wake up the MCU from deep-sleep mode. Providing that the
clock source for the USART must be IRC8M or LXTAL.
This bit is reserved in USART1.
0
UEN
USART enable
0: USART prescaler and outputs disabled
1: USART prescaler and outputs enabled
18.4.2. Control register 1 (USART_CTL1)
Address offset: 0x04
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADDR[7:0]
RTEN
Reserved
MSBF
DINV
TINV
RINV
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STRP
LMEN
STB[1:0]
CKEN
CPL
CPH
CLEN
Reserved
LBDIE
LBLEN
ADDM
Reserved
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:24
ADDR[7:0]
Address of the USART terminal
These bits give the address of the USART terminal.
In multiprocessor communication during mute mode or deep-sleep mode, this is
used for wakeup with address match detection. The received frame, the MSB of
which is equal to 1, will be compared to these bits. When the ADDM bit is reset,
only the ADDR[3:0] bits are used to compare.
In normal reception, these bits are also used for character detection. The whole
received character (8-bit) is compared to the ADDR[7:0] value and AMF flag is set