Must be kept at reset value.
Receive enable acknowledge flag.
This bit, which is set/reset by hardware, reflects the receive enable state of the
USART core logic.
0: The USART core receiving logic has not been enabled.
1: The USART core receiving logic has been enabled.
This bit is reserved in USART1.
Transmit enable acknowledge flag
This bit, which is set/reset by hardware, reflects the transmit enable state of the
USART core logic.
0: The USART core transmitting logic has not been enabled.
1: The USART core transmitting logic has been enabled.
Wakeup from deep-sleep mode flag
0: No wakeup from deep-sleep mode
1: Wakeup from Deep-sleep mode. An interrupt is generated if WUFIE=1 in the
USART_CTL2 register and the MCU is in Deep-sleep mode.
This bit is set by hardware when a wakeup event, which is defined by the WUM bit
field, is detected.
Cleared by writing a 1 to the WUC in the USART_INTC register.
This bit can also be cleared when UESM is cleared.
This bit is reserved in USART1.
Receiver wakeup from mute mode
This bit is used to indicate if the USART is in mute mode.
0: Receiver in active mode
1: Receiver in mute mode
It is cleared/set by hardware when a wakeup/mute sequence (address or IDLEIE)
is recognized, which is selected by the WAKE bit in the USART_CTL0 register.
This bit can only be set by writing 1 to the MMCMD bit in the USART_CMD register
when wakeup on IDLEIE mode is selected.
Send break flag
0: No break character is transmitted
1: Break character will be transmitted
This bit indicates that a send break character was requested.
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