Set by software, by writing 1 to the SBKCMD bit in the USART_CMD register.
Cleared by hardware during the stop bit of break transmission.
ADDR match flag
0: ADDR does not match the received character
1: ADDR matches the received character, an interrupt is generated if AMIE=1 in
the USART_CTL0 register.
Set by hardware, when the character defined by ADDR [7:0] is received.
Cleared by writing 1 to the AMC in the USART_INTC register.
Busy flag
0: USART reception path is idle.
1: USART reception path is working.
Must be kept at reset value.
End of block flag
0: End of Block not reached
1: End of Block (number of characters) reached. An interrupt is generated if the
EBIE=1 in the USART_CTL1 register.
Set by hardware when the number of received bytes (from the start of the block,
including the prologue) is equal or greater than BLEN + 4.
Cleared by writing 1 to EBC bit in USART_INTC register.
This bit is reserved in USART1.
Receiver timeout flag
0: Timeout value not reached.
1: Timeout value reached without any data reception. An interrupt is generated if
RTIE bit in the USART_CTL1 register is set.
Set by hardware when the RT value, programmed in the USART_RT register has
lapsed without any communication.
Cleared by writing 1 to RTC bit in USART_INTC register.
The timeout corresponds to the CWT or BWT timings in smartcard mode.
This bit is reserved in USART1.
CTS level
This bit equals to the inverted level of the nCTS input pin.
0: nCTS input pin is in high level.
1: nCTS input pin is in low level.
CTS change flag.
0: No change occurred on the nCTS status line.
1: A change occurred on the nCTS status line. An interrupt will occur if the CTSIE
bit is set in USART_CTL2.
Set by hardware when the nCTS input toggles.
Cleared by writing 1 to CTSC bit in USART_INTC register.
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