0: LIN Break is not detected.
1: LIN Break is detected. An interrupt will occur if the LBDIE bit is set in
USART_CTL1
Set by hardware when the LIN break is detected.
Cleared by writing 1 to LBDC bit in USART_INTC register.
This bit is reserved in USART1.
Transmit data register empty.
0: Data is not transferred to the shift register.
1: Data is transferred to the shift register. An interrupt will occur if the TBEIE bit is
set in USART_CTL0.
Set by hardware when the content of the USART_TDATA register has been
transferred into the transmit shift register or writing 1 to TXFCMD bit of the
USART_CMD register.
Cleared by a write to the USART_TDATA.
Transmission completed.
0: Transmission is not completed.
1: Transmission is complete. An interrupt will occur if the TCIE bit is set in
USART_CTL0.
Set by hardware if the transmission of a frame containing data is completed and if
the TBE bit is set.
Cleared by writing 1 to TCC bit in USART_INTC register.
Read data buffer not empty.
0: Data is not received.
1: Data is received and ready to be read. An interrupt will occur if the RBNEIE bit is
set in USART_CTL0.
Set by hardware when the content of the receive shift register has been transferred
to the USART_RDATA.
Cleared by reading the USART_RDATA or writing 1 to RXFCMD bit of the
USART_CMD register.
IDLE line detected flag
0: No Idle line is detected.
1: Idle line is detected. An interrupt will occur if the IDLEIE bit is set in
USART_CTL0.
Set by hardware when an Idle line is detected. It will not be set again until the
RBNE bit has been set itself.
Cleared by writing 1 to IDLEC bit in USART_INTC register.
Overrun error
0: No overrun error is detected.
1: Overrun error is detected. An interrupt will occur if the RBNEIE bit is set in
USART_CTL0. In multibuffer communication, an interrupt will occur if the ERRIE
bit is set in USART_CTL2.
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