GigaDevice Semiconductor GD32F3x0 - Page 480

GD32F3x0 User Manual
480
This bit is reserved in USART1.
19:18
Reserved
Must be kept at reset value.
17
AMC
ADDR match clear
Writing 1 to this bit clears the AMF bit in the USART_STAT register.
16:13
Reserved
Must be kept at reset value.
12
EBC
End of block clear
Writing 1 to this bit clears the EBF bit in the USART_STAT register.
This bit is reserved in USART1.
11
RTC
Receiver timeout clear
Writing 1 to this bit clears the RTF flag in the USART_STAT register.
This bit is reserved in USART1.
10
Reserved
Must be kept at reset value.
9
CTSC
CTS change clear
Writing 1 to this bit clears the CTSF bit in the USART_STAT register.
8
LBDC
LIN break detected clear
Writing 1 to this bit clears the LBDF flag in the USART_STAT register.
This bit is reserved in USART1.
7
Reserved
Must be kept at reset value.
6
TCC
Transmission complete clear
Writing 1 to this bit clears the TC bit in the USART_STAT register.
5
Reserved
Must be kept at reset value.
4
IDLEC
Idle line detected clear
Writing 1 to this bit clears the IDLEF bit in the USART_STAT register.
3
OREC
Overrun error clear
Writing 1 to this bit clears the ORERR bit in the USART_STAT register.
2
NEC
Noise detected clear
Writing 1 to this bit clears the NERR bit in the USART_STAT register.
1
FEC
Frame error flag clear
Writing 1 to this bit clears the FERR bit in the USART_STAT register
0
PEC
Parity error clear
Writing 1 to this bit clears the PERR bit in the USART_STAT register.
18.4.10. Receive data register (USART_RDATA)
Address offset: 0x24
Reset value: Undefined