GigaDevice Semiconductor GD32F3x0 - Page 481

GD32F3x0 User Manual
481
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
RDATA[8:0]
r
Bits
Fields
Descriptions
31:9
Reserved
Must be kept at reset value.
8:0
RDATA[8:0]
Receive data value
The received data character is contained in these bits.
The value read in the MSB (bit 7 or bit 8 depending on the data length) will be the
received parity bit, if receiving with the parity is enabled (PCEN bit set to 1 in the
USART_CTL0 register).
18.4.11. Transmit data register (USART_TDATA)
Address offset: 0x28
Reset value: Undefined
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
TDATA[8:0]
rw
Bits
Fields
Descriptions
31:9
Reserved
Must be kept at reset value.
8:0
TDATA[8:0]
Transmit data value.
The transmit data character is contained in these bits.
The value written in the MSB (bit 7 or bit 8 depending on the data length) will be
replaced by the parity, when transmitting with the parity is enabled (PCEN bit set to
1 in the USART_CTL0 register).
This register must be written only when TBE bit in USART_STAT register is set.
18.4.12. USART receive FIFO control and status register (USART_RFCS)
Address offset: 0xD0
Reset value: 0x0000 0400