GigaDevice Semiconductor GD32F3x0 - Page 482

GD32F3x0 User Manual
482
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RFFINT
RFCNT[2:0]
RFF
RFE
RFFIE
RFEN
Reserved
ELNACK
r_w0
r
r
r
rw
rw
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15
RFFINT
Receive FIFO full interrupt flag
14:12
RFCNT[2:0]
Receive FIFO counter number
11
RFF
Receive FIFO full flag
0: Receive FIFO not full
1: Receive FIFO full
10
RFE
Receive FIFO empty flag
0: Receive FIFO not empty
1: Receive FIFO empty
9
RFFIE
Receive FIFO full interrupt enable
0: Receive FIFO full interrupt disable
1: Receive FIFO full interrupt enable
8
RFEN
Receive FIFO enable
This bit can be set when UESM = 1.
0: Receive FIFO disable
1: Receive FIFO enable
7:1
Reserved
Must be kept at reset value.
0
ELNACK
Early NACK when smartcard mode is selected.
The NACK pulse occurs 1/16 bit time earlier when the parity error is detected.
0: Early NACK disable when smartcard mode is selected
1: Early NACK enable when smartcard mode is selected
This bit is reserved in USART1.