GigaDevice Semiconductor GD32F3x0 - Page 504

GD32F3x0 User Manual
504
5:0
I2CCLK[5:0]
I2C peripheral clock frequency
I2CCLK[5:0] should be the frequency of input APB1 clock in MHz which is at least
2.
000000 - 000001: Not allowed
000010 - 110110: 2 MHz~54 MHz
110111 - 111111: Not allowed due to the limitation of APB1 clock
Note: In I2C standard mode, the frequencies of APB1 must be equal or greater
than 2MHz. In I2C fast mode, the frequencies of APB1 must be equal or greater
than 8MHz. In I2C fast mode plus, the frequencies of APB1 must be equal or
greater than 24MHz.
19.4.3. Slave address register 0 (I2C_SADDR0)
Address offset: 0x08
Reset value: 0x0000 0000
This register can be accessed by half-word (16-bit) or word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDFOR
MAT
Reserved
ADDRESS[9:8]
ADDRESS[7:1]
ADDRES
S0
rw
rw
rw
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15
ADDFORMAT
Address format for the I2C slave
0: 7-bit address
1: 10-bit address
14:10
Reserved
Must be kept at reset value.
9:8
ADDRESS[9:8]
Highest two bits of a 10-bit address
7:1
ADDRESS[7:1]
7-bit address or bits 7:1 of a 10-bit address
0
ADDRESS0
Bit 0 of a 10-bit address
19.4.4. Slave address register 1 (I2C_SADDR1)
Address offset: 0x0C
Reset value: 0x0000 0000
This register can be accessed by half-word (16-bit) or word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16