GigaDevice Semiconductor GD32F3x0 - Page 550

GD32F3x0 User Manual
550
20.5.8. I I2S control register (SPI_I2SCTL)
Address offset: 0x1C
Reset value: 0x0000 0000
This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
I2SSEL
I2SEN
I2SOPMOD[1:0]
PCMSMO
D
Reserved
I2SSTD[1:0]
CKPL
DTLEN[1:0]
CHLEN
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rw
rw
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rw
Bits
Fields
Descriptions
31:12
Reserved
Must be kept at reset value.
11
I2SSEL
I2S mode selection
0: SPI mode
1: I2S mode
This bit should be configured when SPI mode or I2S mode is disabled.
10
I2SEN
I2S enable
0: Disable I2S
1: Enable I2S
This bit is not used in SPI mode.
9:8
I2SOPMOD[1:0]
I2S operation mode
00: Slave transmission mode
01: Slave reception mode
10: Master transmission mode
11: Master reception mode
This bit should be configured when I2S mode is disabled.
This bit is not used in SPI mode.
7
PCMSMOD
PCM frame synchronization mode
0: Short frame synchronization
1: long frame synchronization
This bit has a meaning only when PCM standard is used.
This bit should be configured when I2S mode is disabled.
This bit is not used in SPI mode.
6
Reserved
Must be kept at reset value.
5:4
I2SSTD[1:0]
I2S standard selection
00: I2S Phillips standard
01: MSB justified standard