GigaDevice Semiconductor GD32F3x0 - Page 549

GD32F3x0 User Manual
549
RCRC[15:0]
r
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15:0
RCRC[15:0]
RX CRC value
When the CRCEN bit of SPI_CTL0 is set, the hardware computes the CRC value
of the received bytes and saves them in RCRC register. If the data frame format is
set to 8-bit data, CRC calculation is based on CRC8 standard, and saves the value
in RCRC[7:0], when the data frame format is set to 16-bit data, CRC calculation is
based on CRC16 standard, and saves the value in RCRC[15:0].
The hardware computes the CRC value after each received bit, when the TRANS
is set, a read to this register could return an intermediate value.
This register is reset when the CRCEN bit in SPI_CTL0 register or the SPIxRST bit
in RCU reset register is set.
20.5.7. TX CRC register (SPI_TCRC)
Address offset: 0x18
Reset value: 0x0000 0000
This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TCRC[15:0]
r
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15:0
TCRC[15:0]
TX CRC value
When the CRCEN bit of SPI_CTL0 is set, the hardware computes the CRC value
of the transmitted bytes and saves them in TCRC register. If the data frame format
is set to 8-bit data, CRC calculation is based on CRC8 standard, and saves the
value in TCRC[7:0], when the data frame format is set to 16-bit data, CRC
calculation is based on CRC16 standard, and saves the value in TCRC[15:0].
The hardware computes the CRC value after each transmitted bit, when the
TRANS is set, a read to this register could return an intermediate value. The
different frame formats (LF bit of the SPI_CTL0) will get different CRC values.
This register is reset when the CRCEN bit in SPI_CTL0 register or the SPIxRST bit
in RCU reset register is set.