GigaDevice Semiconductor GD32F3x0 - Page 548

GD32F3x0 User Manual
548
SPI_DATA[15:0]
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15:0
SPI_DATA[15:0]
Data transfer register
The hardware has two buffers, including transmission buffer and reception buffer.
Write data to SPI_DATA will save the data to transmission buffer and read data
from SPI_DATA will get the data from reception buffer. When the data frame format
is set to 8-bit data, the SPI_DATA [15:8] is forced to 0 and the SPI_DATA [7:0] is
used for transmission and reception, transmission buffer and reception buffer are
8-bits. If the Data frame format is set to 16-bit data, the SPI_DATA [15:0] is used
for transmission and reception, transmission buffer and reception buffer are 16-bit.
20.5.5. CRC polynomial register (SPI_CRCPOLY)
Address offset: 0x10
Reset value: 0x0000 0007
This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CRCPOLY[15:0]
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15:0
CRCPOLY[15:0]
CRC polynomial register
This register contains the CRC polynomial and it is used for CRC calculation. The
default value is 0007h.
20.5.6. RX CRC register (SPI_RCRC)
Address offset: 0x14
Reset value: 0x0000 0000
This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0