GigaDevice Semiconductor GD32F3x0 - Page 547

GD32F3x0 User Manual
547
register followed by a read access to the SPI_STAT register.
5
CONFERR
SPI configuration error
0: No configuration fault occurs.
1: Configuration fault occurred. (In master mode, the NSS pin is pulled low in NSS
hardware mode or SWNSS bit is low in NSS software mode.)
This bit is set by hardware and cleared by a read or write operation on the
SPI_STAT register followed by a write access to the SPI_CTL0 register.
This bit is not used in I2S mode.
4
CRCERR
SPI CRC error bit
0: The SPI_RCRC value is equal to the received CRC data at last.
1: The SPI_RCRC value is not equal to the received CRC data at last.
This bit is set by hardware and is able to be cleared by writing 0.
This bit is not used in I2S mode.
3
TXURERR
Transmission underrun error bit
0: No transmission underrun error occurs.
1: Transmission underrun error occurs.
This bit is set by hardware and cleared by a read operation on the SPI_STAT
register.
This bit is not used in SPI mode.
2
I2SCH
I2S channel side
0: The next data needs to be transmitted or the data just received is channel left.
1: The next data needs to be transmitted or the data just received is channel right.
This bit is set and cleared by hardware.
This bit is not used in SPI mode, and has no meaning in the I2S PCM mode.
1
TBE
Transmit buffer empty
0: Transmit buffer is not empty.
1: Transmit buffer is empty.
0
RBNE
Receive buffer not empty
0: Receive buffer is empty.
1: Receive buffer is not empty.
20.5.4. Data register (SPI_DATA)
Address offset: 0x0C
Reset value: 0x0000 0000
This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0