GigaDevice Semiconductor GD32F3x0 - Page 586

GD32F3x0 User Manual
586
Reserved
G5P3
G5P2
G5P1
G5P0
G4P3
G4P2
G4P1
G4P0
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
G3P3
G3P2
G3P1
G3P0
G2P3
G2P2
G2P1
G2P0
G1P3
G1P2
G1P1
G1P0
G0P3
G0P2
G0P1
G0P0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:24
Reserved
Must be kept at reset value
23:0
GxPy
Channel pin mode
This bit is set and cleared by software.
0: Pin GxPy is not a channel pin
1: Pin GxPy is a channel pin
22.4.9. Group control register(TSI_GCTL)
Address offset: 0x30
Reset value: 0x0000 0000
This register can be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
GC5
GC4
GC3
GC2
GC1
GC0
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
GE5
GE4
GE3
GE2
GE1
GE0
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:24
Reserved
Must be kept at reset value
21:16
GCx
Group complete
This bit is set by hardware when charge-transfer sequence for an enabled group is
complete. It is cleared by hardware when a new charge-transfer sequence starts.
0: Charge-transfer for group x is not complete
1: Charge-transfer for group x is complete
15:6
Reserved
Must be kept at reset value
5:0
GEx
Group enable
This bit is set and cleared by software.
0: Group x is disabled
1: Group x is enabled