GigaDevice Semiconductor GD32F3x0 - Page 587

GD32F3x0 User Manual
587
22.4.10. Group x cycle number registers(TSI_GxCYCN)(x= 0..5)
Address offset: 0x30 + 0x04 *(x + 1)
Reset value: 0x0000 0000
This register can be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
CYCN[13:0]
rw
Bits
Fields
Descriptions
31:14
Reserved
Must be kept at reset value
13:0
CYCN[13:0]
Cycle number
These bits reflect the cycle number for a group as soon as a charge-transfer
sequence completes. They are cleared by hardware when a new charge-transfer
sequence starts.
22.4.11. Control register1 (TSI_CTL1)
Address offset: 0x300
Reset value: 0x0000 0000
This register can be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
ECDIV[2:1]
Reserved
CTCDIV[
3]
Reserved
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
Bits
Fields
Descriptions
31:30
Reserved
Must be kept at reset value
29:28
ECDIV[2:1]
Extend Charge clock(ECCLK) division factor.
ECCLK in TSI is divided from HCLK and ECDIV defines the division factor.
0x0: f
ECCLK
=f
HCLK
0x1: f
ECCLK
=f
HCLK
/2
0x2: f
ECCLK
=f
HCLK
/3
0x3: f
ECCLK
=f
HCLK
/4