GigaDevice Semiconductor GD32F3x0

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GD32F3x0 User Manual

588

0x4: f

ECCLK

HCLK

0x5: f

ECCLK

HCLK

0x6: f

ECCLK

HCLK

0x7: f

ECCLK

HCLK

Note:ECDIV[2:1] are located in TSI_CTL1 and ECDIV[0] is located in TSI_CTL0.

27:25

Reserved

Must be kept at reset value

CTCDIV[3]

Charge Transfer clock(CTCLK) division factor.

CTCLK in TSI is divided from HCLK and CTCDIV defines the division factor.

0000: f

CTCLK

HCLK

0001: f

CTCLK

HCLK

0010: f

CTCLK

HCLK

0011: f

CTCLK

HCLK

….

0111: f

CTCLK

HCLK

/128

1000: f

CTCLK

HCLK

/256

1001: f

CTCLK

HCLK

/512

….

1110: f

CTCLK

HCLK

/16384

1111: f

CTCLK

HCLK

/32768

Note: CTCDIV[3] is located in TSI_CTL1 and CTCDIV[2:0] are located in

TSI_CTL0.

23:0

Reserved

Must be kept at reset value

Main Page

Table of Contents2
List of Figures15
List of Table21
System and Memory Architecture23
Arm ® Cortex ® -M4 Processor23
Figure 1-1. the Structure of the Cortex -M4 Processor23
System Architecture24
Memory Map25
Figure 1-2. Series System Architecture of Gd32F3X0 Series25
Table 1-1. Memory Map of Gd32F3X0 Series26
Bit-Banding28
On-Chip SRAM Memory28
On-Chip Flash Memory29
Boot Configuration29
Table 1-2. Flash Module Organization29
I / O Compensation Cell30
Table 1-3. Boot Modes30
System Configuration Registers (SYSCFG)31
System Configuration Register 0 (SYSCFG_CFG0)31
EXTI Sources Selection Register 0 (SYSCFG_EXTISS0)32
EXTI Sources Selection Register 1 (SYSCFG_EXTISS1)33
EXTI Sources Selection Register 2 (SYSCFG_EXTISS2)34
EXTI Sources Selection Register 3 (SYSCFG_EXTISS3)36
System Configuration Register 2 (SYSCFG_CFG2)37
I / O Compensation Control Register (SYSCFG_CPSCTL)38
Device Electronic Signature39
Memory Density Information39
Unique Device ID (96 Bits)39
Flash Memory Controller (FMC)41
Overview41
Characteristics41
Function Overview41
Flash Memory Architecture41
Table 2-1. Base Address and Size for Flash Memory41
Read Operations42
Unlock the FMC_CTL Register42
Page Erase42
Mass Erase43
Figure 2-1. Process of Page Erase Operation43
Figure 2-2. Process of the Mass Erase Operation44
Main Flash Programming45
Option Byte Erase46
Figure 2-3. Process of the Word Programming Operation46
Option Byte Programming47
Option Byte Description47
Table 2-2. Option Byte47
Page Erase/Program Protection48
Security Protection49
Table 2-3. OB_WP Bit for Pages Protected49
Register Definition50
Wait State Register (FMC_WS)50
Unlock Key Register (FMC_KEY)50
Option Byte Unlock Key Register (FMC_OBKEY)51
Status Register (FMC_STAT)51
Control Register (FMC_CTL)52
Address Register (FMC_ADDR)53
Option Byte Status Register (FMC_OBSTAT)54
Write Protection Register (FMC_WP)54
Wait State Enable Register (FMC_WSEN)55
Product ID Register (FMC_PID)55
Power Management Unit (PMU)57
Overview57
Characteristics57
Function Overview57
Figure 3-1. Power Supply Overview57
Backup Domain58
VDD58
DD DDA Power Domain59
Figure 3-2. Waveform of the por / PDR59
Figure 3-3. Waveform of the LVD Threshold60
Power Domain61
Power Saving Modes61
Table 3-1. Power Saving Mode Summary63
Register Definition65
Control Register (PMU_CTL)65
Control and Status Register (PMU_CS)67
Reset and Clock Unit (RCU)70
Reset Control Unit (RCTL)70
Overview70
Function Overview70
Clock Control Unit (CCTL)71
Overview71
Figure 4-1. the System Reset Circuit71
Figure 4-2. Clock Tree72
Characteristics73
Function Overview73
Figure 4-3. HXTAL Clock Source73
Figure 4-4. HXTAL Clock Source in Bypass Mode74
Table 4-1. Clock Source Select76
Table 4-2. Core Domain Voltage Selected in Deep-Sleep Mode77
Register Definition78
Control Register0 (RCU_CTL0)78
Configuration Register 0 (RCU_CFG0)79
Interrupt Register (RCU_INT)83
APB2 Reset Register (RCU_APB2RST)86
APB1 Reset Register (RCU_APB1RST)87
AHB Enable Register (RCU_AHBEN)89
APB2 Enable Register (RCU_APB2EN)91
APB1 Enable Register (RCU_APB1EN)92
Backup Domain Control Register (RCU_BDCTL)94
Reset Source /Clock Register (RCU_RSTSCK)96
AHB Reset Register (RCU_AHBRST)97
Configuration Register 1 (RCU_CFG1)99
Configuration Register 2 (RCU_CFG2)100
Control Register 1 (RCU_CTL1)101
Additional Clock Control Register (RCU_ADDCTL)101
Additional Clock Interrupt Register (RCU_ADDINT)102
APB1 Additional Enable Register (RCU_ADDAPB1EN)103
APB1 Additional Reset Register (RCU_ADDAPB1RST)104
Voltage Key Register (RCU_VKEY)104
Deep-Sleep Mode Voltage Register (RCU_DSV)105
Clock Trim Controller (CTC)106
Overview106
Characteristics106
Function Overview106
REF Sync Pulse Generator107
CTC Trim Counter107
Figure 5-1. CTC Overview107
Frequency Evaluation and Automatically Trim Process108
Figure 5-2. CTC Trim Counter108
Software Program Guide109
Register Definition110
Control Register 0 (CTC_CTL0)110
Control Register 1 (CTC_CTL1)111
Status Register (CTC_STAT)112
Interrupt Clear Register (CTC_INTC)114
Interrupt/Event Controller (EXTI)116
Overview116
Characteristics116
Interrupts Function Overview116
Table 6-1. NVIC Exception Types in Cortex-M4116
Table 6-2. Interrupt Vector Table117
External Interrupt and Event (EXTI) Block Diagram119
External Interrupt and Event Function Overview119
Figure 6-1. Block Diagram of EXTI119
Table 6-3. EXTI Source120
Register Definition121
Interrupt Enable Register (EXTI_INTEN)121
Event Enable Register (EXTI_EVEN)121
Rising Edge Trigger Enable Register (EXTI_RTEN)122
Falling Edge Trigger Enable Register (EXTI_FTEN)122
Software Interrupt Event Register (EXTI_SWIEV)123
Pending Register (EXTI_PD)123
General-Purpose and Alternate-Function I/Os (GPIO)125
Overview125
Characteristics125
Function Overview125
GPIO Pin Configuration126
Figure 7-1. Basic Structure of of a General-Pupose I/O126
Table 7-1. GPIO Configuration Table126
Alternate Functions (AF)127
Additional Functions127
Input Configuration127
Figure 7-2. Basic Structure of Input Configuration127
Output Configuration128
Analog Configuration128
Figure 7-3. Basic Structure of Output Configuration128
Alternate Function (AF) Configuration129
Figure 7-4. Basic Structure of Analog Configuration129
Figure 7-5. Basic Structure of Alternate Function Configuration129
GPIO Locking Function130
GPIO Single Cycle Toggle Function130
GPIO very High Speed Drive Capability130
Register Definition131
Port Control Register (Gpiox_Ctl, X=A131
Port Output Mode Register (Gpiox_Omode, X=A132
Port Output Speed Register 0 (Gpiox_Ospd0, X=A134
Port Pull-Up/Down Register (Gpiox_Pud, X=A136
Port Input Status Register (Gpiox_Istat, X=A137
Port Output Control Register (Gpiox_Octl, X=A138
Port Bit Operate Register (Gpiox_Bop, X=A138
Port Configuration Lock Register (Gpiox_Lock, X=A,B)139
Alternate Function Selected Register 0 (Gpiox_Afsel0, X=A,B,C)140
Alternate Function Selected Register 1 (Gpiox_Afsel1, X=A,B,C)141
Bit Clear Register (Gpiox_Bc, X=A142
Port Bit Toggle Register (Gpiox_Tg, X=A142
Port Output Speed Register 1 (Gpiox_Ospd1, X=A143
Cyclic Redundancy Checks Management Unit (CRC)144
Overview144
Characteristics144
Figure 8-1. Block Diagram of CRC Calculation Unit144
Function Overview145
Register Definition146
Data Register (CRC_DATA)146
Free Data Register (CRC_FDATA)146
Control Register (CRC_CTL)147
Initialization Data Register (CRC_IDATA)147
Polynomial Register (CRC_POLY)148
Direct Memory Access Controller (DMA)149
Overview149
Characteristics149
Block Diagram150
Function Overview150
DMA Operation150
Figure 9-1. Block Diagram of DMA150
Table 9-1. DMA Transfer Operation151
Peripheral Handshake152
Arbitration152
Figure 9-2. Handshake Mechanism152
Address Generation153
Circular Mode153
Memory to Memory Mode153
Channel Configuration153
Interrupt154
Figure 9-3. DMA Interrupt Logic154
Table 9-2. Interrupt Events154
DMA Request Mapping155
Figure 9-4. DMA Request Mapping156
Table 9-3. DMA Requests for each Channel157
Register Definition158
Interrupt Flag Register (DMA_INTF)158
Interrupt Flag Clear Register (DMA_INTC)158
Channel X Control Register (Dma_Chxctl)159
Channel X Counter Register (Dma_Chxcnt)161
Channel X Peripheral Base Address Register (Dma_Chxpaddr)162
Channel X Memory Base Address Register (Dma_Chxmaddr)162
Debug (DBG)164
Overview164
Serial Wire Debug Port Overview164
Pin Assignment164
JEDEC-106 ID Code164
Debug Hold Function Overview165
Debug Support for Power Saving Mode165
Debug Support for TIMER, I2C, RTC, WWDGT and FWDGT165
Register Definition166
ID Code Register (DBG_ID)166
Control Register 0 (DBG_CTL0)166
Control Register 1 (DBG_CTL1)168
Analog to Digital Converter (ADC)170
Overview170
Characteristics170
Pins and Internal Signals171
Figure 11-1. ADC Module Block Diagram171
Table 11-1. ADC Internal Input Signals171
Table 11-2. ADC Input Pins Definition171
Function Overview172
Foreground Calibration Function172
Dual Clock Domain Architecture173
ADCON Enable173
Routine Sequence173
Operation Modes173
Figure 11-2. Single Operation Mode173
Figure 11-3. Continuous Operation Mode174
Figure 11-4. Scan Operation Mode, Continuous Disable175
Figure 11-5. Scan Operation Mode, Continuous Enable175
Conversion Result Threshold Monitor Function176
Data Storage Mode176
Figure 11-6. Discontinuous Operation Mode176
Sample Time Configuration177
Figure 11-7. Data Storage Mode of 12-Bit Resolution177
Figure 11-8. Data Storage Mode of 10-Bit Resolution177
Figure 11-9. Data Storage Mode of 8-Bit Resolution177
Figure 11-10. Data Storage Mode of 6-Bit Resolution177
External Trigger Configuration178
DMA Request178
ADC Internal Channels178
Table 11-3. External Trigger Source for ADC178
ADC Interrupts179
Programmable Resolution (DRES)179
Table 11-4. T CONV Timings Depending on Resolution179
On-Chip Hardware Oversampling180
Figure 11-11. 20-Bit to 16-Bit Result Truncation180
Figure 11-12. Numerical Example with 5-Bits Shift and Rounding180
Table 11-5. Maximum Output Results for N and M Combimations (Grayed Values Indicates Truncation)181
Register Definition183
Status Register (ADC_STAT)183
Control Register 0 (ADC_CTL0)183
Control Register 1 (ADC_CTL1)185
Sampling Time Register 0 (ADC_SAMPT0)187
Sampling Time Register 1 (ADC_SAMPT1)187
Watchdog High Threshold Register (ADC_WDHT)188
Watchdog Low Threshold Register (ADC_WDLT)189
Routine Sequence Register0(ADC_RSQ0)189
Routine Sequence Register1(ADC_RSQ1)190
Routine Sequence Register 2 (ADC_RSQ2)190
Routine Data Register (ADC_RDATA)191
Oversampling Control Register (ADC_OVSAMPCTL)191
Digital-To-Analog Converter (DAC)194
Overview194
Characteristic194
Figure 12-1. DAC Block Diagram194
Function Overview195
DAC Enable195
DAC Output Buffer195
DAC Data Configuration195
DAC Trigger195
Table 12-1. DAC I/O Description195
Table 12-2. External Triggers of DAC195
DAC Workflow196
DAC Noise Wave196
Figure 12-2. DAC LFSR Algorithm196
DAC Output Calculate197
DMA Function197
Figure 12-3. DAC Triangle Noise Wave197
Registers Definition198
Control Register (DAC_CTL)198
Software Trigger Register (DAC_SWT)199
DAC 12-Bit Right-Aligned Data Holding Register(DAC_R12DH)200
DAC 12-Bit Left-Aligned Data Holding Register(DAC_L12DH)200
DAC 8-Bit Right-Aligned Data Holding Register (DAC_R8DH)201
DAC Data Output Register (DAC_DO)201
DAC Status Register (DAC_STAT)201
Comparator (CMP)203
Overview203
Characteristic203
Function Overview203
CMP Clock and Reset204
CMP I/O Configure204
Figure 13-1. CMP Block Diagram of Gd32F3X0 Series204
CMP Operating Mode205
CMP Hysteresis205
CMP Register Write Protection205
Figure 13-2. CMP Hysteresis205
CMP Registers206
Control/Status Register (CMP_CS)206
Watchdog Timer (WDGT)210
Free Watchdog Timer (FWDGT)210
Overview210
Characteristics210
Function Overview210
Figure 14-1. Free Watchdog Timer Block Diagram210
Table 14-1. Min/Max FWDGT Timeout Period at 40 Khz (IRC40K)212
Register Definition213
Window Watchdog Timer (WWDGT)217
Overview217
Characteristics217
Function Overview217
Figure 14-2. Window Watchdog Timer Block Diagram217
Figure 14-3. Window Watchdog Timer Timing Diagram218
Table 14-2. Min-Max Timeout Value at 54 Mhz219
Register Definition220
Real-Time Clock (RTC)222
Overview222
Characteristics222
Function Overview223
Block Diagram223
Clock Source and Prescalers223
Figure 15-1. Block Diagram of RTC223
Shadow Registers Introduction224
Configurable and Field Maskable Alarm224
RTC Initialization and Configuration225
Calendar Reading226
Resetting the RTC227
RTC Shift Function227
RTC Reference Clock Detection228
RTC Smooth Digital Calibration229
Time-Stamp Function231
Tamper Detection231
Calibration Clock Output232
Alarm Output232
RTC Power Saving Mode Management233
RTC Interrupts233
Table 15-1. RTC Power Saving Mode Management233
Table 15-2. RTC Interrupts Control233
Register Definition234
Time Register (RTC_TIME)234
Date Register (RTC_DATE)234
Control Register (RTC_CTL)235
Status Register (RTC_STAT)237
Prescaler Register (RTC_PSC)239
Alarm 0 Time and Date Register (RTC_ALRM0TD)239
Write Protection Key Register (RTC_WPK)241
Sub Second Register (RTC_SS)241
Shift Function Control Register (RTC_SHIFTCTL)241
Time of Time Stamp Register (RTC_TTS)242
Date of Time Stamp Register (RTC_DTS)243
Sub Second of Time Stamp Register (RTC_SSTS)243
High Resolution Frequency Compensation Register (RTC_HRFC)244
Tamper Register (RTC_TAMP)245
Alarm 0 Sub Second Register (RTC_ALRM0SS)247
Backup Registers (Rtc_Bkpx) (X = 0248
Timer (Timerx)250
Table 16-1. Timers (Timerx) Are Devided into Six Sorts250
Advanced Timer (Timerx ,X=0)251
Overview251
Characteristics251
Block Diagram252
Figure 16-1. Advanced Timer Block Diagram252
Function Overview253
Figure 16-2. Timing Chart of Internal Clock Divided by 1253
Figure 16-3. Timing Chart of PSC Value Change from 0 to 2254
Figure 16-4. Timing Chart of up Counting Mode, PSC=0/2255
Figure 16-5. Timing Chart of up Counting Mode, Change Timerx_Car on the Go256
Figure 16-6. Timing Chart of down Counting Mode, PSC=0/2257
Figure 16-7. Timing Chart of down Counting Mode, Change Timerx_Car on the Go257
Figure 16-8. Timing Chart of Center-Aligned Counting Mode259
Figure 16-9. Repetition Counter Timing Chart of Center-Aligned Counting Mode260
Figure 16-10. Repetition Counter Timing Chart of up Counting Mode260
Figure 16-11. Repetition Counter Timing Chart of down Counting Mode261
Figure 16-12. Channel Input Capture Principle262
Figure 16-13. Output-Compare under Three Modes264
Figure 16-14. EAPWM Timechart265
Figure 16-15. CAPWM Timechart265
Table 16-2. Complementary Outputs Controlled by Parameters266
Figure 16-16. Complementary Output with Dead-Time Insertion268
Figure 16-17. Output Behavior in Response to a Break(the Break High Active)269
Table 16-3. Counting Direction in Different Quadrature Decoder Mode269
Figure 16-18. Counter Behavior with CI0FE0 Polarity Non-Inverted in Mode 2270
Figure 16-19. Counter Behavior with CI0FE0 Polarity Inverted in Mode 2270
Figure 16-20. Hall Sensor Is Used to BLDC Motor270
Figure 16-21. Hall Sensor Timing between Two Timers272
Table 16-4. Slave Mode Example Table272
Figure 16-22. Restart Mode273
Figure 16-23. Pause Mode273
Figure 16-24. Event Mode274
Figure 16-25. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99274
Figure 16-26. TIMER0 Master/Slave Mode Timer Example275
Figure 16-27. Triggering TIMER0 with Enable Signal of TIMER1276
Figure 16-28. Triggering TIMER0 and TIMER1 with Timer1'S CI0 Input277
Register Definition279
General Level0 Timer (Timerx, X=1, 2)306
Overview306
Characteristics306
Block Diagram307
Figure 16-29. General Level 0 Timer Block Diagram307
Function Overview308
Figure 16-30. Timing Chart of Internal Clock Divided by 1308
Figure 16-31. Timing Chart of PSC Value Change from 0 to 2309
Figure 16-32. Timing Chart of up Counting Mode, PSC=0/2310
Figure 16-33. Timing Chart of up Counting Mode, Change Timerx_Car on the Go311
Figure 16-34. Timing Chart of down Counting Mode, PSC=0/2311
Figure 16-35. Timing Chart of down Counting Mode, Change Timerx_Car on the Go312
Figure 16-36. Center-Aligned Counter Timechart313
Figure 16-37. Channels Input Capture Principle315
Figure 16-38. Output-Compare under Three Modes317
Figure 16-39. EAPWM Timechart317
Figure 16-40. CAPWM Timechart317
Table 16-5. Examples of Slave Mode319
Figure 16-41. Restart Mode320
Figure 16-42. Pause Mode320
Figure 16-43. Event Mode320
Figure 16-65. Pause Mode320
Figure 16-66. Event Mode320
Figure 16-44. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99321
Table 16-6. Timerx(X=1,2) Interconnection322
Register Definition323
General Level2 Timer (Timerx, X=13)348
Overview348
Characteristics348
Figure 16-45. General Level2 Timer Block Diagram348
Figure 16-46. Timing Chart of Internal Clock Divided by 1349
Figure 16-47. Timing Chart of PSC Value Change from 0 to 2350
Figure 16-48. Timing Chart of up Counting Mode, PSC=0/2351
Figure 16-49. Timing Chart of up Counting Mode, Change Timerx_Car on the Go351
Figure 16-50. Channel Input Capture Principle352
Figure 16-51. Output-Compare under Three Modes354
Figure 16-52. PWM Mode Timechart354
Figure 16-53. General Level3 Timer Block Diagram367
Figure 16-54. Timing Chart of Internal Clock Divided by 1368
Figure 16-55. Timing Chart of PSC Value Change from 0 to 2369
Figure 16-56. Timing Chart of up Counting Mode, PSC=0/2370
Figure 16-57. Timing Chart of up Counting Mode, Change Timerx_Car on the Go371
Figure 16-58. Repetition Counter Timing Chart of up Counting Mode372
Figure 16-59. Channel Input Capture Principle373
Figure 16-60. Output-Compare under Three Modes375
Figure 16-61. PWM Mode Timechart375
Table 16-7. Complementary Outputs Controlled by Parameters377
Figure 16-62. Complementary Output with Dead-Time Insertion378
Figure 16-63. Output Behavior in Response to a Break(the Break High Active)379
Table 16-8. Slave Mode Example Table379
Figure 16-64. Restart Mode380
Figure 16-67. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99381
Table 16-9. Timerx(X=14) Interconnection382
Figure 16-68. General Level4 Timer Block Diagram404
Figure 16-69. Timing Chart of Internal Clock Divided by 1405
Figure 16-70. Timing Chart of PSC Value Change from 0 to 2406
Figure 16-71. Timing Chart of up Counting Mode, PSC=0/2407
Figure 16-72. Timing Chart of up Counting Mode, Change Timerx_Car on the Go408
Figure 16-73. Repetition Counter Timing Chart of up Counting Mode409
Figure 16-74. Channel Input Capture Principle410
Figure 16-75. Output-Compare under Three Modes412
Figure 16-76. PWM Mode Timechart412
Table 16-10. Complementary Outputs Controlled by Parameters414
Figure 16-77. Complementary Output with Dead-Time Insertion415
Figure 16-78. Output Behavior in Response to a Break (the Break High Active)416
Figure 16-79. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60417
Figure 16-80. Basic Timer Block Diagram434
Figure 16-81. Timing Chart of Internal Clock Divided by 1435
Figure 16-82. Timing Chart of PSC Value Change from 0 to 2436
Figure 16-83. Timing Chart of up Counting Mode, PSC=0/2437
Figure 16-84. Timing Chart of up Counting Mode, Change Timerx_Car on the Go437
Figure 17-1. IFRP Output Timechart 1444
Figure 17-2. IFRP Output Timechart 2445
Figure 17-3. IFRP Output Timechart 3445
Figure 18-1. USART Module Block Diagram448
Table 18-1. Description of USART Important Pins448
Figure 18-2. USART Character Frame (8 Bits Data and 1 Stop Bit)449
Table 18-2. Configuration of Stop Bits449
Figure 18-3. USART Transmit Procedure451
Figure 18-4. Oversampling Method of a Receive Frame Bit (OSB=0)452
Figure 18-5. Configuration Step When Using DMA for USART Transmission453
Figure 18-6. Configuration Step When Using DMA for USART Reception454
Figure 18-7. Hardware Flow Control between Two Usarts454
Figure 18-8. Hardware Flow Control455
Figure 18-9. Break Frame Occurs During Idle State456
Figure 18-10. Break Frame Occurs During a Frame457
Figure 18-11. Example of USART in Synchronous Mode457
Figure 18-12. 8-Bit Format USART Synchronous Waveform (CLEN=1)458
Figure 18-13. Irda SIR ENDEC Module458
Figure 18-14. Irda Data Modulation459
Figure 18-15. ISO7816-3 Frame Format460
Figure 18-16. USART Receive FIFO Structure462
Table 18-3. USART Interrupt Requests463
Figure 18-17. USART Interrupt Mapping Diagram464
Figure 19-1. I2C Module Block Diagram483
Table 19-1. Definition of I2C-Bus Terminology (Refer to the I2C Specification of Philips Semiconductors)484
Figure 19-2. Data Validation485
Figure 19-3. START and STOP Signal485
Figure 19-4. Clock Synchronization486
Figure 19-5. SDA Line Arbitration486
Figure 19-6. I2C Communication Flow with 7-Bit Address487
Figure 19-7. I2C Communication Flow with 10-Bit Address (Master Transmit)487
Figure 19-8. I2C Communication Flow with 10-Bit Address (Master Receive)487
Figure 19-9. Programming Model for Slave Transmitting (10-Bit Address Mode)489
Figure 19-10. Programming Model for Slave Receiving (10-Bit Address Mode)490
Figure 19-11. Programming Model for Master Transmitting (10-Bit Address Mode)492
Figure 19-12. Programming Model for Master Receiving Using Solution a (10-Bit Address Mode)494
Figure 19-13. Programming Model for Master Receiving Mode Using Solution B (10-Bit Address Mode)496
Table 19-2. Event Status Flags499
Table 19-3. Error Flags499
Figure 20-1. Block Diagram of SPI513
Table 20-1. SPI Signal Description513
Figure 20-2. SPI Timing Diagram in Normal Mode514
Table 20-2. Quad-SPI Signal Description514
Figure 20-3. SPI Timing Diagram in Quad-SPI Mode (CKPL=1, CKPH=1, LF=0)515
Table 20-3. NSS Function in Slave Mode515
Table 20-4. NSS Function in Master Mode516
Table 20-5. SPI Operating Modes516
Figure 20-4. a Typical Full-Duplex Connection517
Figure 20-5. a Typical Simplex Connection (Master: Receive, Slave: Transmit)518
Figure 20-6. a Typical Simplex Connection (Master: Transmit Only, Slave: Receive)518
Figure 20-7. a Typical Bidirectional Connection518
Figure 20-8. Timing Diagram of TI Master Mode with Discontinuous Transfer520
Figure 20-9. Timing Diagram of TI Master Mode with Continuous Transfer520
Figure 20-10. Timing Diagram of TI Slave Mode521
Figure 20-11. Timing Diagram of NSS Pulse with Continuous Transmit522
Figure 20-12. Timing Diagram of Write Operation in Quad-SPI Mode523
Figure 20-13. Timing Diagram of Read Operation in Quad-SPI Mode524
Figure 20-14. Block Diagram of I2S527
Table 20-6. SPI Interrupt Requests527
Figure 20-15. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)528
Figure 20-16. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)529
Figure 20-17. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)529
Figure 20-18. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)529
Figure 20-19. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)529
Figure 20-20. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)529
Figure 20-21. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)530
Figure 20-22. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)530
Figure 20-23. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)530
Figure 20-24. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)530
Figure 20-25. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)531
Figure 20-26. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)531
Figure 20-27. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)531
Figure 20-28. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)531
Figure 20-29. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)531
Figure 20-30. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)531
Figure 20-31. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)532
Figure 20-32. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)532
Figure 20-33. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)532
Figure 20-34. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)532
Figure 20-35. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)533
Figure 20-36. PCM Standard Short Frame Synchronization Mode Timing Diagram534
Figure 20-37. PCM Standard Short Frame Synchronization Mode Timing Diagram534
Figure 20-38. PCM Standard Short Frame Synchronization Mode Timing Diagram534
Figure 20-39. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)534
Figure20-40. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)534
Figure 20-41. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)534
Figure 20-42. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)534
Figure 20-43. PCM Standard Long Frame Synchronization Mode Timing Diagram534
Figure20-44. PCM Standard Long Frame Synchronization Mode Timing Diagram534
Figure 20-45. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)535
Figure 20-46. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)535
Figure 20-47. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)535
Figure 20-48. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)535
Figure 20-49. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)536
Figure 20-50. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)536
Figure 20-51. Block Diagram of I2S Clock Generator536
Table 20-7. I2S Bitrate Calculation Formulas536
Figure 20-52. I2S Initialization Sequence537
Table 20-8. Audio Sampling Frequency Calculation Formulas537
Table 20-9. Direction of I2S Interface Signals for each Operation Mode537
Figure 20-53. I2S Master Reception Disabling Sequence540
Table 20-10. I2S Interrupt542
Figure 21-1. HDMI-CEC Controller Block Diagram555
Figure 21-2. Start Bit556
Figure 21-3. Valid Data Bit556
Table 21-1. Data Bit Timing Parameter Table556
Figure 21-4. Signal Free Time557
Figure 21-5. Error Bit Period558
Figure 21-6. Bit Period Long Error559
Figure 21-7. Transmission Error Detection560
Table 21-2. Error Handling Timing Parameter Table560
Table 21-3. TERR Timing Parameter Table561
Figure 22-1. Block Diagram of TSI Module571
Figure 22-2. Block Diagram of Sample Pin and Channel Pin572
Table 22-1. Pin and Analog Switch State in a Charge-Transfer Sequence573
Figure 22-3. Voltage of a Sample Pin During Charge-Transfer Sequence574
Figure 22-4. FSM Flow of a Charge-Transfer Sequence575
Table 22-2. Duration Time of Extend Charge State in each Cycle576
Table 22-3. Spread Spectrum Deviation Base on HCLK Period577
Table 22-4. TSI Errors and Flags578
Table 22-5. TSI Pins578
Figure 23-1. USBFS Block Diagram590
Table 23-1. USBFS Signal Description590
Figure 23-2. Connection with Host or Device Mode591
Figure 23-3. Connection with OTG Mode592
Figure 23-4. State Transition Diagram of Host Port592
Figure 23-5. HOST Mode FIFO Space in SRAM597
Figure 23-6. Host Mode FIFO Access Register Map597
Figure 23-7. Device Mode FIFO Space in SRAM598
Figure 23-8. Device Mode FIFO Access Register Map598
Table 23-2. USBFS Global Interrupt603
Table 24-1. Revision History663

GigaDevice Semiconductor GD32F3x0 - Page 588

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