Intel
ยฎ
EP80579 Integrated Processor Product LineโReal Time Clock (RTC) Interface
Intel
ยฎ
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
195 Order Number: 320068-005US
โขC
parasitic
= crystalโs parasitic capacitance. This capacitance is created by the
existence of two electrode plates and the dielectric constant of the crystal blank
inside the crystal part. See the crystalโs specification to obtain this value.
Ideally, C1 and C2 can be chosen such that C1 = C2. Using the equation of C
load
above,
the values of C1 and C2 can be calculated to give the best accuracy (closest to
32.768 KHz) of the RTC circuit at room temperature. However, C2 can be chosen such
that C2 > C1, and then C1 can be trimmed to obtain the 32.768 KHz.
In certain conditions, both the C1 and C2 values can be shifted away from the
theoretical values calculated from the above equation to obtain the closest oscillation
frequency to 32.768 KHz. When C1 and C2 are smaller than the theoretical values, the
RTC oscillation frequency will be higher.
The following example illustrates the use of practical values of C1 and C2 in the case
that theoretical values cannot guarantee the accuracy of the RTC in a low temperature
condition:
Example:
According to the required 12.5 pF load capacitance of a typical crystal that is used with
EP80579, the calculated values of C1 = C2 is 15 pF at room temperature (25
ยฐ
C) yields
a 32.768KHz oscillation.
At 0
ยฐ
C, the frequency stability of the crystal gives โ23 ppm (assuming the circuit has 0
ppm at 25
ยฐ
C). This makes the RTC circuit oscillate at 32.767246 KHz instead of
32.768 KHz.
If the values of C1 and C2 are chosen as 6.8 pF instead of 10 pF, the RTC will oscillate
at a higher frequency at room temperature (+23 ppm), but this configuration of C1 and
C2 makes the circuit oscillate closer to 32.768 KHz at 0
ยฐ
C. The 6.8 pF value of C1 and
C2 is the practical value.
Note: The temperature dependency of the crystal frequency is a parabolic relationship (ppm/
degree squared). The effect of changing the crystalโs frequency when operating at 0ยฐ C
(25ยฐ C below room temperature) is the same when operating at 50ยฐ C (25ยฐ C above
room temperature). See the crystalโs datasheet for more details.
15.1.3 RTC Layout Considerations
Since the RTC circuit is very sensitive and requires highly accurate oscillation,
reasonable care must be taken during layout and routing of the RTC circuit. Some
recommendations are:
โข Reduce trace capacitance by minimizing the RTC trace length. A trace length of less
than 1 in. on each branch (from the crystalโs terminal to the RTCXn signals) is
recommended. Keep routing on the RTC circuit basic to simplify the trace length
measurement and increase accuracy on calculating trace capacitances. Trace
capacitance depends on the trace width and dielectric constant of the boardโs
material. On FR-406, a trace of 5 mils has approximately 2 pF per inch.
โข Reduce trace signal coupling by avoiding routing of adjacent PCI signals close to
RTCX1 and RTCX2.
โข Use of a ground guard plane is highly recommended.
โข The oscillatorโs Vcc must be clean; use a filter, such as an RC low-pass, or a ferrite
inductor.
C
trace
trace length 2 pf per inchโข=