Intel EP80579

Intel
®
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 281
Layout Checklist—Intel
®
EP80579 Integrated Processor Product Line
27.3 CK410 Layout Checklist
For additional information, see the CK410 Clock Synthesizer/Driver Specification and
the component’s datasheet.
TSYNC_TX_SNAP Zo = 50 Ω +/- 10%
Miscellaneous I/O Interface
JTAG
TMS Zo = 50
Ω +/- 10%
See Section 26.3.1, “JTAG
Routing Guidelines”.
TDI Zo = 50
Ω +/- 10%
See Section 26.3.1, “JTAG
Routing Guidelines”.
TDO Zo = 50
Ω +/- 10%
See Section 26.3.1, “JTAG
Routing Guidelines”.
TCK Zo = 50
Ω +/- 10%
See Section 26.3.1, “JTAG
Routing Guidelines”.
TRST# Zo = 50
Ω +/- 10%
See Section 26.3.1, “JTAG
Routing Guidelines”.
BPM3_IN Zo = 50
Ω +/- 10%
See Section 26.3.1, “JTAG
Routing Guidelines”.
BPM4_PRDY_OUT Zo = 50
Ω +/- 10%
See Section 26.3.1, “JTAG
Routing Guidelines”.
BPM5_PREQ_IN Zo = 50
Ω +/- 10%
See Section 26.3.1, “JTAG
Routing Guidelines”.
BPM[3:0] Zo = 50
Ω +/- 10%
See Section 26.3.1, “JTAG
Routing Guidelines”.
Miscellaneous Pins
PME# Zo = 50
Ω +/- 10%
PCIRST# Zo = 50 Ω +/- 10%
SPKR Zo = 50
Ω +/- 10%
Reserved Pins
Reserved[20:0] Zo = 50
Ω +/- 10%
No Connect Pins
Note: (All No Connect Pins should be left un-connected)
NC_SUS_TWO Zo = 50
Ω +/- 10%
NC_TWO Zo = 50
Ω +/- 10%
NC7 Zo = 50
Ω +/- 10%
NC[22:9] Zo = 50
Ω +/- 10%
NC[38:34] Zo = 50
Ω +/- 10%
NC[48:40] Zo = 50 Ω +/- 10%
NC[57:50] Zo = 50
Ω +/- 10%
Table 97. Layout Checklist (Sheet 13 of 13)
Signal Name
Trace Geometry and
Impedance
Length Requirements Comments