Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 261
Debug Port Design Guide—Intel
®
EP80579 Integrated Processor Product Line
Figure 154 shows another method for termination that is equally valid. This is a
termination prior to the end receiver where the maximum routing length of the signal
must be less than the length of (D) + (C). (C) must be less than 200ps.
In both Figure 153 and Figure 154, there may be other devices on the (A) or (D)
routing of the signal (if called for within this document).
26.3 Routing Guidelines
This section provides implementation details specific to these designs only and takes
priority over any discrepancies existing between this document and any other Debug
Port Design Guide.
For EP80579 systems, VTAP refers (within this section) to the 1.2V EP80579 core
voltage.
26.3.1 JTAG Routing Guidelines
26.3.1.1 TDI-TDO Routing Guidelines
Route TDI and TDO as shown in Figure 155.
Figure 153. Termination After Last Receiver
Device
Receiver
A
B
V
Device
Driver
Figure 154. Termination Prior to Last Receiver
Device
Receiver
DC
V
Device
Driver

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English