Intel
ยฎ
EP80579 Integrated Processor Product LineโSystem Memory Interface (DIMM)
Intel
ยฎ
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
111 Order Number: 320068-005US
9.0 System Memory Interface (DIMM)
This chapter contains topologies and routing guidelines for the EP80579 DDR2 system
memory interface. It provides the DDR2 implementation solution for system designs
requiring two DIMMs, unbuffered or registered, operating at 400/533/667/800 MT/s
speed rates. This chapter
does not provide guidelines for memory down design
implementations.
9.1 Terminology and Definitions
9.2 Supported Configurations
Table 27 shows the various DDR2 device technologies supported by the EP80579.
Table 26. DDR Terminology
Acronym Description/Comment
Unbuffered memory
Memory that does not contain buffers or registers located on the module. The memory
controller directly communicates with the memory devices.
Buffered memory
Memory that contains buffers on the module that re-drive signals from the memory
controller to the memory devices.
Note: EP80579 does not support this feature.
Registered memory
Memory that contains registers on the module that register and re-drives the signals
from the memory controller to the memory devices.
Self-refresh Memory technology that is built in the DRAM that refreshes on its own.
Page size
Minimum number of column locations on any row and are accessed by a single
ACTIVATE command
DRAM devices Multiple DRAM devices together make up a DIMM
Rank
Defines a set of DRAM chips (on a module) comprising 8 byte wide (64/32 bits) data,
or 9 bytes (72/40 bits) with ECC.
All devices in a Rank are connected by a single chip select. The actual memory size is
not defined. Single-sided memory modules are always single-rank. Double-sided
unbuffered and registered DIMMs are always dual-rank.
Table 27. Supported DDR2 Device Densities and Widths
Technology
Support
Device Density Device Width
256 Mb x8 Supported
512 Mb x8 Supported
1 Gb x8 Supported
2 Gb x8 Supported
4 Gb x8 Not Supported