Intel
ยฎ
EP80579 Integrated Processor Product LineโPCI Express* Interface
Intel
ยฎ
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
141 Order Number: 320068-005US
Table 50 and Figure 91 summarize the layout routing solution space to a PCI Express
connector. In this case, EP80579 is a receiver and the PCI Express connector is a
transmitter. LT must be routed on the same layer.
โข L1 is the EP80579 breakout region.
โข L2 starts from the edge of the EP80579 breakout region to the PCI Express
connector.
โข LT is the main routing section that is from the EP80579 pin to the connector.
Table 49. PCI Express Connector Routing (EP80579 Transmit)
Parameter Routing Guidelines Figure
Signal Group PEA0_Tn[7:0], PEA0_Tp[7:0] -
Reference Plane Ground Referenced -
Layer Assignment
Layers 3 or 8 (stripline)
Layers 1 or 10 (microstrip)
-
Characteristic Trace Impedance (Zo) 90 ฮฉ ยฑ10% (Differential) -
Nominal Trace Width
4.5 mils (stripline)
4.75 mils (microstrip)
Figure 87
Figure 88
Nominal Trace Spacing within a pair from
edge to edge
5.5 mils (stripline)
5.25 mils (microstrip)
Figure 87
Figure 88
Nominal Trace Spacing from edge of one
differential pair to edge of another
differential pair
The greater of:
โข 18 mils or 3x dielectric thickness (stripline)
โข 20 mils or 3x dielectric thickness
(microstrip)
Figure 87
Figure 88
Trace Length L1, L1โโ EP80579 Breakout
region and to AC CAP
Min = 0.5 in.
Max = 2.5 in.
Figure 90
Trace Length L2, L2โ + L3, L3โโ AC CAP to
PCI Express connector
Min = 4.5 in.
Max = 15.5 in.(stripline)
Max = 15.0 in. (microstrip)
Figure 90
Trace Length LTโ EP80579 pin to PCI
Express connector
LT = L1 + L2 + L3 Figure 90
AC CapacitorโAC CAP 0.1 ฮผF Figure 90
Length Tuning Requirements
Routing must remain on the same layer.
Maximum number of vias is 4.
LT-LTโ = ยฑ5 mils
Figure 90
Figure 90. PCI Express Connector Routing (EP80579 Transmit)
EP80579
PCI
Express*
Connector
L1
L2
L3
AC CAP
LT = L1 + L2 + L3
L1'
L2'
L3'
AC CAP