Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line—Low Pin Count (LPC) Interface
Intel
®
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
190 Order Number: 320068-005US
14.3.3 Motherboard Placement Consideration
Optimum routing can typically be achieved by placing the TPM close to the EP80579 or
other LPC peripherals (e.g., Firmware Hub, Super I/O).
The TPM is a security device that must be shielded as much as possible from physical
access. In high-security implementations, there are a number of mechanisms that can
be used to detect or prevent physical system intrusion, but such mechanisms are
beyond the scope of this design guide. However, convenience of physical access to the
TPM can be minimized by placing the TPM behind the memory DIMMs. In an ATX or
Figure 126. TPM 1.1/EP80579 Block Diagram
Figure 127. TPM 1.2/EP80579 Block Diagram
LAD[0]
LAD[2]
LAD[3]
LAD[1]
SERIRQ
SUS_STAT#
EP80579
LFRAME#
LAD0
LAD2
LAD3
LAD1
SERIRQ
LPCPD#
TPM 1.1
LFRAME#
Clock Chip
LCLK
CLK33
PLTRST#
LRESET#
LAD0
LAD2
LAD3
LAD1
SERIRQ
SUS_STAT#
LFRAME#
LAD0
LAD2
LAD3
LAD1
SERIRQ
LPCPD#
TPM 1.2
LFRAME#
Clock Chip
LCLK
CLK33
PLTRST#
LRESET#
SMBDATA
SMDATA
SMBCLK
SMCLK
XTALI
XTALO
32 KHz
Crystal
EP80579

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English