Intel EP80579

Intel
®
EP80579 Integrated Processor Product Line—System Memory Interface (Memory Down)
Intel
®
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
345 Order Number: 320068-005US
B.6.6 DC Bias Signals
The DC bias signals consist of DDR_SLWCRES, DDR_RCOMPX, DDR_CRES[2:0],
DDV_CRES, and DDR_VREF. The routing guidelines for these signals are described in
Section B.6.6.1 and Section B.6.6.2.
Table B-31. DDR2 Address/Command Signal Group Routing Guidelines
Parameter Routing Guidelines Figure
Signal Group
DDR_MA[14:0], DDR_BA[2:0], DDR_RAS#,
DDR_CAS#, DDR_WE#, DDR_CS[0]#, DDR_CKE[0],
DDR_ODT[0]
Reference Plane Ground Referenced
Layer Assignment • Signals must be routed on the same layer
Characteristic Trace Impedance (Zo) 45 Ω ±10%
Nominal Trace Width See Stackup
Nominal Trace Spacing (e2e) 15 mils
Clearance from other signals 20 mils (min)
Board Routing Guidelines
Total Trace Length (TTL) = (Lp + L0
+ L1 + L2 + L3 + L4)
Total Trace Length = 2.0 in - 6.0 in
Lp
Package Length:
• See the Intel
®
EP80579 Integrated Processor Product Line
Datasheet for package length information.
L0
Microstrip Break-out:
•Trace Length = 0.5in (max)
L1
Stripline Board Route
• Trace Length = 1.5 in (min) - 4.0 in (max)
L2
Stripline Board Route:
•Trace Length = 0.8in(max)
L3
Stripline Board Route:
•Trace Length = 0.8in(max)
L4
Microstrip Break-in
•Trace Length = 0.5in (max)
L-ECC
ECC Stripline Board Route:
• Trace Length = L2 + L3
TL1 (Stub to Rtt)
Microstrip Route
•Trace Length = 0.4in (max)
On-Board Termination
Termination Resistor (Rtt) 60 Ω ±1% Figure B-27
Routing Length Matching Rules
Inter group signal length matching
Match total length of ADD, CMD, and CTRL signals to
within 20 mils of each other.
(ADD/CMD/CTRL) - to - Clock
Match total length of ADD/CMD/CTRL to Clocks to
within 20 mils
• ADD/CMD/CTRL minimum Length = Clock - 0 mils
• ADD/CMD/CTRL maximum Length = Clock +
20 mils