Intel
®
EP80579 Integrated Processor Product Line—System Memory Interface (Memory Down)
Intel
®
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
337 Order Number: 320068-005US
B.5 Supported Memory Configurations
The EP80579 Memory Controller supports up to 4 GB of 400/533/667/800 MT/s
memory in a one-rank (2 GB) or two-rank (4 GB) configuration. However, since 9
(8 Data +1 ECC) x8 devices are required for each rank, only single rank designs are
reasonably feasible in the memory down implementations. These guidelines support
only one rank memory configurations as listed in Table B-25.
Byte 5
DDR_DQ[40..47],
DDR_DM5, &
DDR_DQS5/DQS5#
Data Byte Lane5
Byte 6
DDR_DQ[48..55],
DDR_DM6, &
DDR_DQS6/DQS6#
Data Byte Lane6
Byte 7
DDR_DQ[56..63],
DDR_DM7, &
DDR_DQS7/DQS7#
Data Byte Lane7
Byte 8
DDR_ECC[0..7],
DDR_DM8,
DDR_DQS8/DQS8#
Data Byte Lane 8 (ECC Check Bits)
Control
Control (CTRL)
DDR_CKE[1:0] Clock Enables
DDR_CS#[1:0] Chip Selects - One chip select per rank
DDR_ODT[1:0] On-Die-Termination
Address & Command
Address / Command
(ADDR/CMD)
DDR_MA[14:0] Memory Address
DDR_BA[2:0] Bank Address (Bank Select)
DDR_RAS# Row Address Select
DDR_CAS# Column Address Select
DDR_WE# Write Enable (Output)
Clocks
Clocks
DDR_CLK[5:0]/
DDR_CLK#[5:0]
Differential Clocks – Three pairs per rank
DC Bias
DC Bias (I/O)
DDR_CRES[2:0]
• DDR_CRES[2:1] - Impedance compensation resistors.
• DDR_CRES[0] - Common return for DDR2 interface
compensation resistors on DDV_CRES,
DDR_SLWCRES and DDR_RCOMPX
DDR_SLWCRES Slew rate compensation for DDR2 interface (Analog)
DDR_RCOMPX Impedance compensation for DDR2 interface
DDV_CRES DDR2 resistor
DDR_VREF Voltage Reference (Analog)
Table B-24. DDR2 Signal Groups (Sheet 2 of 2)
Group Signal Name Description
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