Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 259
Debug Port Design Guide—Intel
®
EP80579 Integrated Processor Product Line
26.2.1 General Debug Port Overview
The debug port is a connection into a target-system environment that provides access
to JTAG, run control, system control, and observation resources.
The XDP is a 60-pin, small form-factor connector, that provides for additional silicon /
system debug resources compared to other debug-port implementations and provides
for expansion for future capabilities.
The EP80579 also provided a consistent, IEEE 1149.1 compliant JTAG Boundary Scan
Chain (BSC) for most interfaces. There are three high-speed interfaces, PCI Express*,
SATA and USB, is not implemented in JTAG boundary scan. These interfaces are used
the XOR Chains. See the Intel
®
EP80579 Integrated Processor Product Line Datasheet
for a detailed signal pin list for BSC and XOR chain.
26.2.2 Debug Port Design Reviews
Intel would be pleased to review your system for debug port design accuracy. Please
contact your Intel field sales representative or Field Applications Engineer (FAE) for a
formal design review of the debug port implementation on your system.
26.2.3 Depopulating XDP for Production Units
At some point there may be a desire to remove the XDP from production units. Intel
recommends that the debug-port real estate and pads remain in place if they need to
be populated for a future problem.
Depopulate all physical devices (connector, termination resistors, jumpers) except:
• Termination of OBSFN_x[0:1] / BPM[4:5]# / PREQ#, PRDY#
• Termination of TCK
• Termination of TDI
• Termination of TMS
• Termination of TRSTn
It is acceptable to replace the standard resistor values with any resistor value between
51 ohm to 1k ohm to reduce bill-of-material items.
Scan Chain
Collection of TAP devices with concurrent TAP state control and serial data
connection. Note that the XDP definition permits more than one scan chain to
be controlled.
TAP IEEE Standard 1149.1 defined Test Access Port.
TAP Master
A device that is designed to control accesses into an IEEE Standard 1149.1
style scan chain and all TAP agents contained within that scan chain. The ITP is
an example of a TAP master.
UP Uni-processor.
VTAP
Operating voltage for the system TAP and TAP Master. For most systems this
voltage is VTT. For systems with out VTT, this will be Vcc.
XDP
eXtended Debug Port - A specific implementation that provides additional
interfaces useful for debug and validation above other debug port
implementations.
XDP-SSA
XDP Second-Side Attach - alternate connector and debug capability for ITP-
XDP, ITP-XDP2.
Table 94. Terms and Definitions
Term Definition

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English