Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 319
System Memory Interface (SODIMM)—Intel
®
EP80579 Integrated Processor Product Line
Table A-4. DDR2 Signal Groups
Group Signal Name Description
Data, Mask, & Strobe
Byte 0
DDR_DQ[0..7],
DDR_DM0, &
DDR_DQS0/DQS0#
Data Byte Lane0
Byte 1
DDR_DQ[8..15],
DDR_DM1, & DQS1/
DDR_DQS1#
Data Byte Lane1
Byte 2
DDR_DQ[16..23],
DDR_DM2, & DQS2/
DDR_DQS2#
Data Byte Lane2
Byte 3
DDR_DQ[24..31],
DDR_DM3, & DQS3/
DDR_DQS3#
Data Byte Lane3
Byte 4
DDR_DQ[32..39],
DDR_DM4, &
DDR_DQS4/DQS4#
Data Byte Lane4
Byte 5
DDR_DQ[40..47],
DDR_DM5, &
DDR_DQS5/DQS5#
Data Byte Lane5
Byte 6
DDR_DQ[48..55],
DDR_DM6, &
DDR_DQS6/DQS6#
Data Byte Lane6
Byte 7
DDR_DQ[56..63],
DDR_DM7, &
DDR_DQS7/DQS7#
Data Byte Lane7
Control
Control
DDR_CKE[1:0] Clock Enables
DDR_CS#[1:0] Chip Selects
DDR_ODT[1:0] On-Die-Termination
Address & Command
Address / Command
DDR_MA[14:0] Memory Address
DDR_BA[2:0] Bank Address (Bank Select)
DDR_RAS# Row Address Select
DDR_CAS# Column Address Select
DDR_WE# Write Enable
Clocks
Clocks
DDR_CLK[1:0]/
DDR_CLK#[1:0]
Differential Clocks
DC Bias
DC Bias (I/O)
DDR_CRES[2:0]
• DDR_CRES[2:1] - Impedance compensation resistors.
• DDR_CRES[0] - Common return for DDR2 interface
compensation resistors on DDV_CRES,
DDR_SLWCRES and DDR_RCOMPX
DDR_SLWCRES Slew rate compensation for DDR2 interface (Analog)
DDR_RCOMPX Impedance compensation for DDR2 interface
DDV_CRES DDR2 resistor
DDR_VREF Voltage Reference (Analog)

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English