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Intel EP80579 Guide
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Intel
®
EP80579 Integrate
d Processor Product Lin
e—Platform System Clock
Inte
l
®
EP80579 Integrated Processo
r Product Line
Platfo
rm Des
ign Guide
May 2010
93
Order Number: 320068-005US
Figure
52.
Deve
lopmen
t Board
Clockin
g Diag
ram
EP80579
IT
P
Por
t
8
0
SI
O
IT
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_
B
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L
K
100M
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OR
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FW
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Z_CLK
FW
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80_33
M
H
Z_C
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CH_33M
H
Z_CLK
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3
MHZ_C
LK
LPC_14M
H
Z_CLK
I
CH_14M
H
Z_CLK
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CH_U
SB
_48MH
Z_C
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8
6
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[
5
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0
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L
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[
5
:
0
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#
SUSCLK
EXP
_SLOT
2_100MH
Z_C
LK
GbE PHY
125MH
Z_C
LK
SA
TA_100M
H
Z_Di
f
f
Me
mor
y
14.318
MHz
SMA
DB
800
TPM
TPM
_33
MH
Z_CLK
D
eve
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opm
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nt
B
oar
d Cl
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ng
EXP
_SLOT
1_100MH
Z_C
LK
PCI
Expr
ess
Sl
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LEB C
onnec
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s
33 M
Hz SE
LEB 33M
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CK
-
410
8.
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92 M
H
z
25M
HZ_C
LK
EXP
_BF1_100MH
Z_C
LK
EXP
_BF2_100MH
Z_C
LK
EXP
_BF3_100MH
Z_C
LK
EXP
_BF4_100MH
Z_C
LK
EXP
_BF5_100MH
Z_C
LK
PCIe
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1
Sl
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2
Sl
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3
Sl
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4
Fanout
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25 M
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Cr
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TDM
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e
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ani
nes
CPU_
0
/
CPU_
0
#
CPU_
2
/
CPU_
2
#
SR
C_4/
SRC_
4
#
SR
C_2/
SRC_
2
#
SR
C_3/
SRC_
3
#
SR
C_1/
SRC_
1
#
PCI
_0
PCI
_1
PCI
_4
PCI
_2
REF
REF
US
B_48
PCI
_3
N
ote
: D
iffe
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92
94
Table of Contents
Table of Contents
3
Revision History
17
Introduction
20
Reference Documentation
20
Reference Documents
20
Acronyms and Terminology
21
System Overview
24
System Architecture Description
24
EP80579 Features
24
EP80579 Feature List
25
Development Board
26
Development Board Block Diagram
26
Development Board Features
28
Development Board Feature List
28
EP80579 External Clock Requirements
30
Baseboard Requirements
32
Development Board Component Placement
32
Development Board Component Placement - Top View
32
Assumptions for System Placement Example
32
Development Board Component Placement - Bottom View
33
PCB Recommended 10-Layer Stack-Up
34
Platform Stack-Up
35
Mounting
36
Development Board Summary
36
Component Quadrant Layout
37
Quadrant Layout (Top View)
37
Quadrant Layout
38
Quadrant Layout (Bottom View)
38
High-Speed Design Concerns
40
Return Path
40
Decoupling Theory
40
Proper Decoupling Capacitor Placement with Respect to Vias
40
Bulk Decoupling
41
High-Frequency Decoupling
41
Serpentine Routing
41
Routing in a Serpentine Manner
41
Serpentine Spacing-Spacing to Reference Plane Height Ratio
41
High Speed Differential Routing Rules
42
Serpentine Line
42
Serpentine Line Rules for Differential Signals
43
Stitching Differential Signals between Layers
43
Tied Together for the same Potential Planes
43
Series Capacitor for Different Potential Planes
43
Stitching Vias Aligned with Signal Vias
43
Stitching for Layer Changes
43
Traces Routed Parallel to Plane
44
Trace Segment Length Equalization, Bend, and Spacing
45
Trace Segment Length
45
Trace Mismatch
45
Trace Mismatch and Compensation
46
Trace Length Mismatch Corners
46
Routing Examples of the Length Compensation #1
46
Routing Examples of the Length Compensation #2
47
DC Blocking Capacitor
47
DC Blocking Capacitor
48
EMI Design Consideration
48
Brief EMI Theory
49
EMI Regulations and Certifications
49
EMI Test Capabilities
49
Spread Spectrum Modulation Profile
49
Spread Spectrum Clocking (SSC)
50
Impact of Spread Spectrum Clocking on Radiated Emissions
50
Cancellation of H-Fields through Inverse Currents
50
Differential Clocking
51
Length Tuning Parameters
51
Length Tuning
52
Signal Length Solution Space with One Strobe
52
Signal Length Solution with Two Strobes
52
Signal-To-Strobe Flight Time Relationships
53
Signal Length Solution Space with Furthest Apart Strobes
53
Signal Length Solution Space with Matched Strobes
53
Flight Time Segment Analysis
54
Total Signal Length with Two Components
54
Package Trace Length Differences
55
Bus Length Tuning Methodology
56
System Bus Tuning
56
Compensating for Package Trace Length Differences
56
Example of PLC Compensation on the Motherboard
56
Common Layout Pit-Falls
57
Signal Parallelism
57
Improper Via Sharing
58
Via Sharing
59
Correct Via Connections
59
Necking down
60
Improper Necking down
60
Correct Necking down
61
Signal Crossing Plane Splits
62
Order Number: 320068-005US May
62
Signals Crossing Plane Splits
63
System Power Delivery Guide
64
Terminology and Definitions
64
Power Supply
65
Power Supply Pins
65
Power Planes
66
Power and Ground Planes
66
Power Requirements
67
Development Board Power Delivery Implementation
67
Power Delivery Guidelines
69
Core Power (VCC_CPU)
69
Development Board Power Delivery Voltage Definitions
69
Core Logic Voltage (V1P2)
70
IA-32 Core Frequency and Power Select (BSEL/V_SEL)
70
DDR2 Voltage (V1P8_DDR)
70
DDR2 Termination Voltage (DDR2_VTT)
70
Voltage (V1P8)
70
Gbe 2.5V (V2P5)
70
Vcc3)
71
Voltage (VCC50)
71
VCCRTC Reference
71
Standby Voltages
71
Auxiliary Voltages
72
Component Power Distribution Guidelines
72
Core Power Distribution Guidelines
72
General Switching Power Supply Design Recommendations
72
Voltage Regulator Multi-Phase Topology Example
72
Voltage Regulator Design Recommendations
73
Buck Voltage Regulator Example
73
High Current Path with Top MOSFET Turned on
73
High Current Path During Abrupt Load Current Changes
74
High Current Path with Top and Bottom Mosfets Turned off (Dead Time)
74
High Current Path with Bottom MOSFET(S) Turned on
75
Power Plane Filter Requirements
77
Processor VCCA Decoupling Circuit Topology
77
Analog/Bandgap Filter Topology
78
Analog and Bandgap Filter Layout Guidelines
79
Analog and Bandgap Filter Frequency Response
79
Analog and Bandgap Filter Components
79
Thermal Power Dissipation
80
Filter Frequency Response Specification
80
Decoupling Recommendations
81
VCCVC (IA-32 Core Power) Decoupling
81
VCC (1.2V Core Logic) Decoupling
81
VCCA[2:1] (1.2V, IA-32 Core PLL Power) Decoupling
81
VCCAPE (1.2V, PCI Express Power) Decoupling
82
VCC18 (1.8V - DDR2) Decoupling
82
VTTDDR (0.9V - DDR2_VTT) Decoupling
82
V1P8_DDR (DIMM) Decoupling (CRB Power Reference)
82
VCC33 (3.3V) Decoupling
82
VCC25 (2.5V Gbe Voltage) Decoupling
82
VCC50 (5.0V Reference) Decoupling
83
VCCPRTC (Battery Power) Decoupling
83
VCC50_SUS (5.0V Standby Logic) Decoupling
83
VCCPSUS (3.3V Standby Logic) Decoupling
83
VCCSUS25 (2.5V Standby Logic) Decoupling
83
VCCSUS1 (1.2V Standby Logic) Decoupling
83
Types of Reset and Wake-Up from Power Saving States
84
Software Controlled Reset
85
CPU (IA-32 Core) Only Reset
85
Reset and Powergood Interface Implementation
85
Power Management and Reset Interface
84
Reset and Powergood Distribution
84
Types of Reset
84
Powergood Implementation
84
Hard Reset Implementation
84
Powergood and Reset Interface
85
Powergood Interface
86
Reset Interface
86
Reset Sequence
87
Power Management
88
Supported Power States
88
Three Basic System Power States
88
Clock Control States
89
Power Sequencing
90
Platform System Clock
91
Platform System Clock Generation
91
CK410 Clock Groups
92
Platform System Clock Reference
92
Ref
92
Development Board Clocking Diagram
93
System Clock Groups
94
HOST_CLK Group
94
Source Shunt Termination
94
Trace Spacing for HOST_CLK Clocks
95
HOST_CLK Routing Guidelines
95
CLK100 (SRC Clock) Group
96
Source Clock Topology to down Devices (Except PCI-E)
97
100 Mhz SRC/SRC# Clock Routing Guidelines for down Devices(Except PCI-E)
97
CLK100 Clock Group (SRC Clock) Topology
98
100 Mhz SRC/SRC# Clock Routing Guidelines for PCI Express Slot/Component
98
CLK33 Group
99
Trace Spacing for 100 Mhz SRC Clocks
99
33 Mhz Clock Relationships
99
Topology for CLK33 to down Devices
100
Trace Spacing for CLK33 (PCICLK) Clock
100
CLK33 Routing Guidelines to EP80579, FWH, and LPC down Devices
100
CLK14 Group
101
Topology for Sharing CLK33 between Two down Devices
101
CLK33 Routing Guidelines for Two down Devices
101
CLK48 Group
102
CLK14 Group Routing Guidelines
102
CK410 General Design Guides
103
Clock Driver Decoupling
103
Topology for CLK14
102
Trace Spacing for CLK14 (REFCLK) Clocks
102
CLK48 Routing Guidelines
103
Clock Power Delivery
104
Decoupling Caps and Ferrite Beads
104
Topology for CLK48 Group
103
Trace Spacing for CLK48 (USBCLK) Clocks
103
Clock Grouping for Decoupling / Filtering
105
CK410 Power Plane Filtering
106
Clock Power Groupings for Decoupling / Filtering
105
Decoupling and Filtering Per Clock Group
106
Ground Flood on Layer 1 Underneath CK410
108
Edge Decoupling Caps - Examples
109
Iref
110
EMI Constraints
110
Decoupling Capacitors Placement and Connectivity
110
DDR Terminology
111
Supported DDR2 Device Densities and Widths
111
System Memory Interface (DIMM)
111
Terminology and Definitions
111
Supported Configurations
111
Supported DRAM Capacity for 64-Bit Mode
112
Supported DRAM Capacity for 32-Bit Mode
112
Rules for Populating DIMM Slots
113
Supported Rank Configurations
113
Supported DDR2 Data Speeds
113
Supported DIMM Populations
113
Supported DDR2 Rank Configurations in Single and Dual DIMM Mode
113
DRAM Addressing
114
256Mb Addressing
114
1Gb Addressing
115
DDR2 DIMM Ordering Overview
116
DDR-DIMM- Implementation
116
Example of One Single-Rank DIMM Population
116
System Memory Design Guidelines
117
Example of Two Single-Rank DIMM Population
117
Example of Dual-Rank DIMM Population
117
DDR2 Signal Groups
118
Package Length Compensation
119
Length Matching and Length Formulas
119
DDR2 Interface System Interconnect
119
Length Matching Formulas between EP80579 and DDR2 DIMM
119
Topologies and Routing Guidelines
120
DDR2 Interfaced System Interconnect
120
Data Signal Daisy Chain Routing Topology
120
Ddr
120
Data and Strobe Signal Group Routing Guidelines
121
Data/Mask/Strobe Signal Routing Topology Diagram
121
Data and Strobe Signal Group Routing Guidelines
122
Differential Clock Signal Mapping
123
Ddr
123
Example Length Matching for a Data Byte Lane
123
EP80579-To-DIMM Interconnect DDR2 Clock Signals
124
Clock Signal Group Routing Guidelines
125
DDR2 Point-To-Point Clock Routing Diagram
125
Clock Signal Group Routing Guidelines
126
DDR2 Control Signal Group Routing Guidelines
127
DDR2 Control Signals- Implementation
127
Write Operation ODT Table
128
Address and Command Signals
129
Read Operation ODT Table
129
DDR2 Address/Command Signal Group Routing Guidelines
130
Reset Pin Requirement
131
DC Bias Signals
131
Address/Command Daisy Chain with Parallel Termination Topology Diagram
130
DDR2 Address/Command Signal Group Routing Guidelines
131
DDR_SLWCRES, DDR_RCOMPX, DDV_CRES, & DDR_CRES0 Routing Topology
132
DDR_CRES1 and DDR_CRES2 Signal Connections
132
DDR_VREF Generation Example Circuit
133
Decoupling Recommendations
134
Order Number: 320068-005US May
135
PCI Express Layout Design Guidelines
136
PCI Express* Interface
135
PCI Express* Interconnect
136
Board Stack-Up Consideration
137
Impedance Requirements
138
Trace Width/Impedance Requirement for Stripline and Microstrip Layers
138
AC Coupling Requirements
139
Via Requirements
139
Recommended PCI Express Stripline Trace Width/Spacing
138
Recommended PCI Express Microstrip Trace Width/Spacing
139
Compensation Resistor Signals Guidelines
140
PCI Express Clocks Routing Guidelines
140
Topology 1 - EP80579 to PCI Express Connector
140
PCI Express Compensation Signal Guidelines
140
PCI Express Connector Routing (EP80579 Transmit)
141
Topology 2 - EP80579 to PCI Express Connector
142
With Logic Analyzer Connector142
142
PCI Express Connector Routing (EP80579 Receive)
142
PCI Express Connector with LAI Connector Routing (EP80579 Transmit)
143
PCI Express Connector with LAI Connector Routing (EP80579 Transmit)
144
Topology 3 - EP80579 to PCI Express down Device
145
PCI Express Connector with LAI Connector Routing (EP80579 Receive)
145
PCI Express down Device Routing (EP80579 Transmit)
146
PCI Express down Device Routing (EP80579 Receive)
147
Topology 4 - EP80579 to PCI Express down Device with Logic Analyzer Connector
148
PCI Express down Device with LAI Connector Routing (EP80579 Transmit)
148
PCI Express down Device with LAI Connector Routing (EP80579 Transmit)
149
Additional Considerations for PCI Express
150
PCI Express I/O Devices
150
Emi
150
PCI Express down Device with LAI Connector Routing (EP80579 Receive)
150
PCI Express (JTAG) Boundary Scan Pins
151
Terminating Unused PCI Express Ports
151
Probing Differential Pairs
151
No Connect Signals for Unused PCI Express Ports
151
Serial ATA (SATA) Interface
152
SATA Interface
152
General Routing and Placement
152
SATA Layout and Routing Example
153
SATA Transmit and Receive Signals - Sata_Txp[1:0], Sata_Txn[1:0], Sata_Rxp[1:0], Sata_Rxn[1:0]
154
Transmit and Receive Routing Guidelines
154
SATA Tx and Rx Signal Routing Topology
155
SATA PCB Routing
156
SATA Trace Separation
157
SATA Trace Length Guidelines and Pair Matching
157
SATA Trace Spacing
157
SATA AC Coupling Requirements
158
SATA General Purpose Signals - SATA1_GP, SATA0_GP
158
SATA Clock Signals - Sata_Clkrefp, Sata_Clkrefn
158
Order Number: 320068-005US May
158
SATA_RBIAS/SATA_RBIAS# Connection
158
Sata_Rbiasp/Sata_Rbiasn Connection
158
SATALED# Implementation
159
SATA Host Connector Placement Considerations
159
SATALED# Circuitry Example
159
SATA_RBIAS/SATA_RBIAS# Routing Summary
159
SATA Cable 90º Bend Height Example
160
SATA Host Connector Placement Region Recommendations
160
SATA Host Connector Placement ATX Area B
161
Terminating Unused SATA Interface
162
Example of Poor Host Connector Placement
162
Minimum Host Connector Placement Spacing (from SATA Specification)
162
Universal Serial Bus (USB) Interface
164
USB Interface
164
Layout Guidelines
164
General Routing and Placement
164
USB Differential Signals - Usbp[1:0], Usbn[1:0]
165
Case 1, USB Routing Guidelines - EP80579 to Connector
165
USB Trace Lengths from Controller to Connector
166
Case 2, USB Routing Guidelines - EP80579 Front Panel Option
166
USB Trace Lengths for EP80579 Front Panel Solution
167
Case 3, USB Routing Guidelines - Optional Front Panel Solution
167
USB Trace Lengths for Optional Front Panel Option
168
Microstrip) Recommended USB Trace Spacing
168
Stripline) Recommended USB Trace Spacing
168
Usb_Rbiasp/Usb_Rbiasn Connection
169
USB 2.0 Trace Length Guidelines
169
Clock Signal -- USB CLK48
170
USB over Current Protection - OC[1:0]
170
Plane Splits, Voids, and Cut-Outs (Anti-Etch)
170
VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)
170
Usb_Rbiasp/Usb_Rbiasn Routing Summary
170
GND Plane Splits, Voids, and Cut-Outs (Anti-Etch)
171
USB Power Line Layout Topology
171
EMI Considerations
171
Common Mode Chokes
171
Good Downstream Power Connection
171
Common Mode Choke
171
Esd
172
Front Panel Solutions
173
Internal USB Cables
173
Motherboard/Pcb Mating Connector
174
Conductor Resistance (Table 6-6 from USB 2.0 Specification)
174
Front Panel Header Schematic
175
Front Panel Header Pin-Out
175
Front Panel Daughter Card
176
Terminating Unused USB Interface
176
Motherboard Front Panel USB Support
176
Smbus 2.0 / Smlink Interface
178
Smbus Design Considerations
178
General Design Considerations
179
High Power/Low Power Mixed Architecture
179
System Management Bus (Smbus) Interface
178
Smbus 2.0/Smlink Interface
178
High Power/Low Power Mixed Suspend/Core Power Well Architecture
179
Calculating the Physical Segment Pull-Up Resistor
180
Enabled System Management Features (Optional)
180
Bus Capacitance Reference Chart
180
Bus Capacitance/Pull-Up Resistor Relationship
180
Enabled System Management Vendors (Optional)
181
Enabled System Management Vendors
181
Development Board System Management Implementation
182
Development Board System Management - Smbus Block Diagram
183
SIO Implementation
184
System Management SIO Implementation
185
Low Pin Count (LPC) Interface
186
LPC Interface
186
LPC Layout
187
General Routing and Placement
187
LPC Interface Routing and Topology
187
LPC Interface Diagram
187
Development Board LPC Interface Block Diagram
188
Topology of LPC Interface
188
Clock Signals -- CLK33
189
Trusted Platform Module (TPM) Guidelines
189
TPM Design Considerations
189
Routing Recommendations
189
Motherboard Placement Consideration
190
TPM 1.1/EP80579 Block Diagram
190
TPM 1.2/EP80579 Block Diagram
190
Firmware Hub (FWH) Guidelines
191
FWH and Flash BIOS Vendors
191
FWH Decoupling
191
FWH INIT# Voltage Compatibility
191
FWH VPP Design Guidelines (Optional)
191
FWH VPP Isolation Circuitry
192
Real Time Clock (RTC) Interface
193
RTC Interface
193
RTC Crystal
193
RTCX1 and SUSCLK Relationship in EP80579
193
External Capacitors
194
External Circuitry for the RTC
194
RTC Routing Summary
194
RTC Layout Considerations
195
RTC External Battery Connection
196
A Schottky Diode Circuit to Connect RTC External Battery
196
Internal Only RTC External RTEST# Circuit
197
Susclk
197
RTEST# External Circuit for the RTC
197
RTC Well Input Strap Requirements
198
Synchronous Peripheral Interface (SPI)
199
Terminating Unused SPI Port
199
SPI Interface General Routing Guidelines
199
Serial Peripheral Interface Signal Description
199
SPI Routing Guidelines
200
Boot BIOS Selection
200
SPI Single Flash Device Routing Summary
200
Serial Flash Vendors
201
SPI Topology (System BIOS Only)
200
Boot-Up Strapping Options (Flash)
201
GPIO Pin Definitions
202
Development Board GPIO Usage
203
Interrupts
204
General Purpose I/O (GPIO) and Interrupt Interface
202
GPIO Signals
202
Interrupt Configurations - APIC Mode
204
Serial Interface Unit (SIU/UART)
206
SIU (UART) Interface
206
SIU Interface Signals
206
SIU Interface Interconnect
207
SIU Interface Interconnect
208
Gigabit Ethernet (Gbe) Interface
209
Gbe MAC/LAN Interface Interconnect
209
Order Number: 320068-005US May
209
Frequency Requirements
210
Gbe MAC Interface Guidelines
210
Gigabit Ethernet Interface Signals
210
Frequencies of All Input Clocks
210
Gbe Controller/Lan Interface Interconnect
210
Gben Pin Table
211
Gbe Interface - LAN Connect Interface Guidelines
215
Gbe Ethernet Interface - RGMII Mode
215
Gbe MAC Serial EEPROM Interface Signals
215
Gbe MAC Management Data Interface Signals
215
Gbe Ethernet Interface - RMII Mode
216
Gbe RGMII Mode Signal Connection Block Diagram
216
Gbe RMII Mode Signal Connection Block Diagram
217
Gbe Transmit and Receive Topology
218
Gbe Transmit Topology
218
Gbe RGMII Transmit Path Clock Topology
219
Gbe RGMII Transmit Path Clock Routing Guidelines
220
Gbe RGMII Transmit Path Data\Control Topology
221
Gbe Receive Topology
222
Gbe RGMII Transmit Path Data\Control Routing Guidelines
222
Gbe RGMII Receive Path Clock Topology
223
Gbe RGMII Receive Path Clock Routing Guidelines
224
Gbe RGMII Receive Path Data/Clock/Control Topology
225
Gbe Serial EEPROM
226
Wake on LAN
226
Gbe Rcomp
226
Gbe RGMII Receive Path Data\Control Routing Guidelines
226
Crosstalk Considerations
227
Pull-Up Termination
227
General Gigabit Ethernet Design Guidelines
227
IEEE 1588-2008 Hardware Assist Interface
229
Input/Output Signal Application
230
Classic Clock Synchronization Example
230
EP80579 IEEE 1588-2008 Hardware Assist Block Diagram
232
Input
233
Outputs
233
Board Design Tips
233
Controller Area Network (CAN) Interface
234
Input/Output Signal Application
235
CAN Physical Interface Example
235
Multipoint Topology
236
Board Design Tips
236
CAN Multipoint Topology
236
Local Expansion Bus (LEB) Interface
237
LEB Chip Select Assignment
237
LEB Memory Size (LEB_SIZE) Strapping
238
LEB Interface Topologies
238
LEB Interface Topology at 33 Mhz
238
Chip Select Topologies
239
Multi-Drop Topology Diagram
239
Multi-Drop Topology Trace Lengths for the Development Board
239
Chip Select Point-To-Point Topology Diagram
240
Chip Select Point-To-Point Topology Routing Guidelines
240
Address Star Topologies
241
Data and Control Star Topology
242
Address Signals Star Topology Diagram
242
Data, and Control Signals Star Topology Diagram
243
Mezzanine Card Interconnect
244
Address, Data and Control Star Topology Routing Guidelines
244
Address, Data, and Control Signals Mezzanine Star Topology Diagram
245
Address, Data and Control Star Topology Routing Guidelines
245
Input/Output Signal Application
246
Design Notes
247
Time Division Multiplex (TDM) Interface
248
Development Board TDM Support
248
SLIC/CODEC Interface
248
Device Connection
248
TDM to SLIC/CODEC Interface Example
249
Input/Output Signal Application
250
Design Notes
250
Synchronous Serial Port (SSP) Interface
251
Development Board SSP Support
251
EP80579 SSP Interface
251
Serial Peripheral Interface (SPI)
252
Microwire* Interface
253
Board Design Tip
253
SSP to Serial Flash Interface Example
253
Sideband Signals
254
Cpuslp_Out#, Init33V_Out#, Nmi, Smi_Out#, Stpclk_Out, Rcin
257
Routing Recommendations for Sideband Signals
257
Debug Port Design Guide
258
Overview
258
Terms and Definitions
258
General Debug Port Overview
259
Debug Port Design Reviews
259
Depopulating XDP for Production Units
259
General Guidelines
260
Termination Resistors
260
Routing Guidelines
261
JTAG Routing Guidelines
261
Termination after Last Receiver
261
Termination Prior to Last Receiver
261
Observation Port Routing Guidelines
262
TDI-TDO Routing
262
Hook Pins Routing Guidelines
263
BPM5 and Bpm3_In Platform Circuit
263
C (SDA/SCL) Routing Guidelines
265
Power
265
System Connection
265
XDP to EP80579 Signal Connections
265
Mechanical Specifications
266
XDP Connector System Keep-Out Diagram
267
Layout Checklist
268
Functional Signal Definitions
268
Signal Type Definitions
268
Layout Checklist
269
CK410 Layout Checklist
281
CK410 Schematic Checklist
282
Schematics Checklist
283
Functional Signal Definitions
283
Signal Type Definitions
283
Schematic Checklist
284
Power Supply Decoupling
310
CK410 Schematic Checklist
312
Reference Design
315
System Memory Interface (SODIMM)
316
Terminology and Definitions
317
Supported Configurations
317
A.2 Supported Configurations
317
Differences between Unbuffered SODIMM and Unbuffered DIMM
317
Supported SODIMM Memory Capacity for 64-Bit Mode
317
DDR Terminology
317
SODIMM System Memory Design Guidelines
318
DDR2 Unbuffered SODIMM and Unbuffered DIMM Pin Comparison Table
318
DDR2 Signal Groups
319
Length Matching Formulas between EP80579 and DDR2 SODIMM
320
DDR2 Interfaced System Interconnect
321
A-6 Data and Strobe Signal Group Routing Guidelines
322
Data/Mask/Strobe Signal Routing Topology Diagram
322
A-7 Clock Signal Group Routing Guidelines
324
DDR2 Point-To-Point Clock Routing Diagram
324
Write Operation ODT Table
325
DDR2 Control Signals- Implementation
326
Read Operation ODT Table
326
DDR2 Control Signal Group Routing Guidelines
327
Address and Command Signals
327
A-12 DDR2 Address/Command Signal Group Routing Guidelines
328
Address/Command with Parallel Termination Topology Diagram
328
DDR_SLWCRES, DDR_RCOMPX, DDV_CRES, & DDR_CRES0 Routing Topology
330
DDR_CRES1 and DDR_CRES2 Signal Connections
330
A.5 Decoupling Recommendations
331
Decoupling Recommendations
331
Clock Delay Programming and Write Levelization
332
DDR_VREF Generation Example Circuit
331
Write Levelization for Dual Rank Configuration
332
System Memory Interface (Memory Down)
333
Terminology and Definitions
333
B-16 DDR Terminology
333
Supported Configurations
334
B.2 Supported Configurations
334
DDR Terminology
334
Supported DDR2 Device Densities and Widths
334
Supported DRAM Capacity for 64-Bit Mode
334
DRAM Addressing
335
B.3 DRAM Addressing
335
512Mb Addressing
335
DDR2 Signal Groups
336
Supported DRAM Capacity for 32-Bit Mode
335
256Mb Addressing
335
1Gb Addressing
336
Supported Memory Configurations
337
Order Number: 320068-005US May
337
Overview and Design Considerations
338
Figures
338
B-25 Memory Configurations Supported by the EP80579
338
B-26 Length Matching Formulas for Memory down Configuration
338
Memory Configurations Supported by the EP80579
338
Length Matching Formulas for Memory down Configuration
338
B-28 Clock Signal Group Routing Guidelines
340
Clock to Memory Device Mapping
340
DDR2 Clock Signal Routing Topology (One Clock for Three Devices)
340
B-29 Data and Strobe Signal Group Routing Guidelines
342
DDR2 Data/DM/Ecc Byte Lane Topology
342
DDR2 Data Strobe Routing (DQS/DQS#) Topology (One Strobe Per Byte Lane)
342
Address and Command Signals
344
DDR2 Address, Command and Control Signal Routing Topology
344
B-31 DDR2 Address/Command Signal Group Routing Guidelines
345
DDR_SLWCRES, DDR_RCOMPX, DDV_CRES, & DDR_CRES0 Routing Topology
346
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User Guide
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Intel EP80579 Specifications
General
Brand
Intel
Model
EP80579
Category
Computer Hardware
Language
English
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