Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 165
Universal Serial Bus (USB) Interface—Intel
®
EP80579 Integrated Processor Product Line
• Keep USB 2.0 signals clear of the core logic set. High current transients are
produced during internal state transitions and can be very difficult to filter out.
• Follow the 20*h general guideline by keeping traces at least 20*(height above the
plane) away from the edge of the plane (Vcc or GND, depending on the plane the
trace is over).
For an example, the stackup height above the plane is 4.5 mils. This calculates to a
spacing requirement of 90 mils from the edge of the plane. This helps prevent the
coupling of the signal onto adjacent wires and also helps prevent free radiation of
the signal from the edge of the PCB.
12.2.2 USB Differential Signals – USBp[1:0], USBn[1:0]
The USB interface has two differential pairs for a total of four signals. Route each pair
differentially as microstrip or stripline. Table 60, Table 61, and Table 62 summarize the
USBp and USBn routing guidelines for three cases:
• Case 1: Table 60 gives the routing guidelines for the USB controller to a connector
on the board. See Figure 109.
• Case 2: Table 61 gives the routing guidelines to implement a front panel option that
uses a cable to a daughter card panel for the USB connector. The choke is on the
main board rather than on the daughter card panel. See Figure 110.
• Case 3: Table 62 gives the routing guidelines to implement a front panel option that
uses a cable to a daughter card panel for the USB connector. In this case, the choke
is on the daughter card panel. See Figure 111.
The front panel design option, Case 2, is made on the board using a 0 Ω resistor.
Putting this resistor on the board required a layer change for the USB signals, which
required simulation. The rear panel design option is similar to Case 1 in that it goes
directly to a connector on the board. The front panel option is more stringent since the
header will be connected to a front panel daughter card through a cable. See Section
12.7, “Front Panel Solutions” on page 173 for more information about front panel
solutions.
Table 60. Case 1, USB Routing Guidelines – EP80579 to Connector (Sheet 1 of 2)
Parameter Routing Guidelines Figure
Signal Group USBp[1:0], USBn[1:0] -
Reference Plane Ground Referenced, Stripline or Microstrip -
Layer Assignment
Layers 1 or 10 (microstrip)
Layers 3 or 8 (stripline)
-
Characteristic Trace Impedance (Zo)
1
90 Ω ±10% (differential) -
Nominal Trace Width
4.75 mils – microstrip
4.5 mils – stripline
Figure 112
Figure 113
Nominal Trace Spacing
Trace Spacing, edge-to-edge:
5.25 mils– microstrip
5.5 mils– stripline
Pair-to-pair spacing, edge to edge: 45 mils
minimum
Spacing to clock signals: 45 mils minimum
Spacing to non-clock signals: 45 mils minimum
Figure 112
Figure 113
Nominal Trace Length
Keep all lengths as short as possible. Length L2
must be as short as possible to keep the choke as
close to the connector as possible.
LT = 2–11 in. – microstrip (differential)
2–10 in. – stripline (differential)
Figure 109

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English