Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 124
System Memory Interface (DIMM)—Intel
®
EP80579 Integrated Processor Product Line
The differential clock pairs must be routed differentially from the EP80579 pin to their
associated DIMM pins and must maintain the correct isolation spacing from other
signals. Additionally, it is important to maintain the correct spacing and length
matching between the pair to protect the differential integrity.
Figure 80 and Table 41 depict the recommended topology and layout routing guidelines
for the DDR2 differential clocks. Route differential pair signals on the same layer.
The clocks are routed point-to-point. No external terminations are required for the
clock signals because they are terminated on the DIMMs.
Figure 79. EP80579-to-DIMM Interconnect DDR2 Clock Signals
DIMM 0
EP80579
DIMM 1
CLK2/CLK2#
Package
Trace
EP80579 Pin
EP80579
Pad
Breakout
Routing
Board
Routing
CLK0/CLK0#
CLK1/CLK1#
CLK3/CLK3#
CLK4/CLK4#
CLK5/CLK5#
A
B
C
L
BREAK
L
ROUTE
L
PKG

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English