Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 222
Gigabit Ethernet (GbE) Interface—Intel
®
EP80579 Integrated Processor Product Line
19.6.2 GbE Receive Topology
19.6.2.1 GbE Receive Clock Topology
Figure 140 shows the routing topology of the GbE Receive clock. The receive clock
topology is for the routing of GbEn_RxCLK (RGMII) or GbEn_CLK (RMII). The routing
guidelines for the Receive Data and Control signals in section Section 19.6.2.2 are
referenced to the Receive clock. Table 85 provides routing guidelines for the Receive
Clock signals.
Table 84. GbE RGMII Transmit Path Data\Control Routing Guidelines
Parameter Routing Constraints
Routing Layer Stripline Microstrip
Reference Plane Ground Reference
Board Trace Impedance 55 Ω 55 Ω
Trace Width 3.75mils (L3/L8) 4.5mils (L1/L10)
Data\Control Spacing (e2e) 12 mils (min) 18 mils (min)
EP80579 Data\Control Tx Breakout
Length (LD\C_Brk_out_tx)
0.5 inch (max) 0.5 inch (max)
Data\Control Tx Board Length
(LD\C_Brd_route_tx)
min =1.0 inch
max = 7.0 inch
min =1.5 inch
max = 8.0 inch
PHY Data\Control Tx Breakin Length
(LD\C_Brk_in_tx)
0.3 inch (max) 0.3 inch (max)
Total Data\Control Tx Routing
(LD\C_total_tx)
LClk_total_tx ± 50 mils
(See Table 83)
LClk_total_tx ± 50 mils
(See Table 83)
Pull Up Resistor T-Line (Lpull_up) 0.4 inch (max) 0.4 inch (max)
Pull Up Resistor (Rpull_up) 1.2 KΩ (5%)) 1.2 KΩ (5%)
Breakout\Breakin Spacing (e2e) 4 mils (min) 4 mils (min)

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English