Intel EP80579

Intel
®
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 128
System Memory Interface (DIMM)—Intel
®
EP80579 Integrated Processor Product Line
9.7.1.3.1 ODT Settings
Table 43 and Table 44 provides the DDR2 Controller and DIMM ODT settings for write
and read operations to/from single-rank (SR) and dual-rank (DR) DIMM modules.
Clearance from other signals 20 mils (min)
Board Routing Guidelines
Total Trace Length (TTL) = (L
PKG
+
L
BREAK
+ L
ROUTE
+ L
D2D
+ L
TERM
)
(TTL of CMD/ADD) + 2.5 in ±5% (See Table 46)
L
PKG
See the Intel
®
EP80579 Integrated Processor Product Line Datasheet
for package length information.
L
BREAK
Max = 0.8 in
L
ROUTE
Calculate from Total Trace Length
L
D2D
Max = 0.8 in
• Trace length skews for the control signal for DIMM-to-DIMM
routing should not exceed 10 mils
L
TERM
Max = 500 mils
• Trace length skews for the control signals to the termination
resistors (L
TERM
) should not exceed 200 mils.
On-Board Termination
Parallel Termination Resistor (Rtt) 60 Ω ±1% Figure 81
Length/Skew Matching Rules
Length Tuning Requirements
• The control signals need to match in length within
± 20 mils of each other.
Table 42. DDR2 Control Signal Group Routing Guidelines (Sheet 2 of 2)
Parameter
Routing Guidelines for 2-DIMM Solution with
ODT
Figure
Table 43. Write Operation ODT Table
DIMM
Module
Write
Target
Controller
Configuration
DIMM 0
Configuration
DIMM 1
Configuration
DIMM 0 DIMM 1 Rank0 Rank1 Rank0 Rank1
SR Empty Rank0 ODT Off 75 Ω n/a n/a n/a
DR Empty Rank0 ODT Off ODT Off 75 Ω n/a n/a
DR Empty Rank1 ODT Off 75 Ω ODT Off n/a n/a
SR SR Rank0 ODT Off ODT Off n/a 75 Ω n/a
SR SR Rank1 ODT Off 75 Ω n/a ODT Off n/a