Intel EP80579

Intel
®
EP80579 Integrated Processor Product Line—System Memory Interface (Memory Down)
Intel
®
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
335 Order Number: 320068-005US
Note: In the 32b mode, all EP80579 unused data bus bits (DQ[63:33]/DQS[7:4]/DM[7:4])
should be pulled high through 10 Kohm resistors.
B.3 DRAM Addressing
Table B-20, Table B-21, Table B-22 and Table B-23 show the DRAM device addressing
for the various DDR2 device technologies and densities supported by the memory
controller.
Note that:
• x4 and x 16 devices are not supported.
• 4Gb and higher device density parts are not supported.
•See Table B-17 for the supported device technologies.
Table B-19. Supported DRAM Capacity for 32-bit Mode
Total DRAM
Capacity
DRAM Technology
Total # of parts
(without ECC)
DRAM
Density
DRAM Part
Width
128 MB 256 Mb x8 4
256 MB 512 Mb x8 4
512 MB 1 Gb x8 4
1GB 2 Gb x8 4
Table B-20. 256Mb Addressing
Configuration
DDR2
32 Mb x 8
# of Banks 4
Bank Address BA0, BA1
Auto Precharge A10
Row Address A0-A12
Column Address A0-A9
Page Size 1KB
Table B-21. 512Mb Addressing
Configuration
DDR2
64 Mb x 8
# of Banks 4
Bank Address BA0, BA1
Auto Precharge A10
Row Address A0-A13
Column Address A0-A9
Page Size 1KB