Intel EP80579

May 2010 Intel
®
EP80579 Integrated Processor Product Line
Order Number: 320068-005US 3
Contents—Intel
®
EP80579 Integrated Processor Product Line
Contents
1.0 Introduction.................................................................................................................................... 20
1.1 Reference Documentation .................................................................................................. 20
1.2 Acronyms and Terminology ................................................................................................21
2.0 System Overview...........................................................................................................................24
2.1 System Architecture Description.........................................................................................24
2.1.1 EP80579 Features.................................................................................................24
2.2 Development Board ............................................................................................................26
2.2.1 Development Board Features ................................................................................28
2.3 EP80579 External Clock Requirements .............................................................................30
3.0 Baseboard Requirements ..............................................................................................................32
3.1 Development Board Component Placement ......................................................................32
3.2 Platform Stack-Up...............................................................................................................35
3.3 Mounting .............................................................................................................................36
4.0 Component Quadrant Layout ........................................................................................................ 37
4.1 Quadrant Layout .................................................................................................................38
5.0 High-Speed Design Concerns .......................................................................................................40
5.1 Return Path.........................................................................................................................40
5.2 Decoupling Theory..............................................................................................................40
5.2.1 Bulk Decoupling .....................................................................................................41
5.2.2 High-Frequency Decoupling ..................................................................................41
5.3 Serpentine Routing .............................................................................................................41
5.4 High Speed Differential Routing Rules ...............................................................................42
5.4.1 Serpentine Line Rules for Differential Signals .......................................................43
5.4.2 Stitching Differential Signals Between Layers .......................................................43
5.4.3 Trace Segment Length Equalization, Bend, and Spacing .....................................45
5.4.4 Trace Mismatch and Compensation ...................................................................... 46
5.4.5 DC Blocking Capacitor...........................................................................................48
5.5 EMI Design Consideration ..................................................................................................48
5.5.1 Brief EMI Theory ....................................................................................................49
5.5.2 EMI Regulations and Certifications .......................................................................49
5.5.3 EMI Test Capabilities ............................................................................................49
5.5.4 Spread Spectrum Clocking (SSC) ........................................................................50
5.5.5 Differential Clocking ..............................................................................................51
5.6 Length Tuning ....................................................................................................................52
5.6.1 Signal-to-Strobe Flight Time Relationships ...........................................................53
5.6.2 Flight Time Segment Analysis ..............................................................................54
5.6.3 Bus Length Tuning Methodology .......................................................................... 56
5.7 System Bus Tuning.............................................................................................................56
5.7.1 Compensating for Package Trace Length Differences ......................................... 56
5.8 Common Layout Pit-Falls ..................................................................................................57
5.8.1 Signal Parallelism .................................................................................................57
5.8.2 Via Sharing ...........................................................................................................59
5.8.3 Necking Down........................................................................................................60