Intel EP80579

Intel
®
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 146
PCI Express* Interface—Intel
®
EP80579 Integrated Processor Product Line
Table 54 and Figure 95 summarize the layout routing solution space to a PCI Express on
board device. In this case, EP80579 is a receiver and the PCI Express device is a
transmitter. LT must be routed on the same layer and the signals must reference one
continuous plane.
• L1 is the EP80579 breakout region.
Table 53. PCI Express Down Device Routing (EP80579 Transmit)
Parameter Routing Guidelines Figure
Signal Group PEA0_Tn[7:0], PEA0_Tp[7:0] -
Reference Plane Ground Referenced -
Layer Assignment
Layers 3 or 8 (stripline)
Layers 1 or 10 (microstrip)
-
Characteristic Trace Impedance (Zo) 90 Ω ±10% (Differential) -
Nominal Trace Width
4.5 mils (stripline)
4.75 mils (microstrip)
Figure 87
Figure 88
Nominal Trace Spacing within a pair from
edge to edge
5.5 mils (stripline)
5.25 mils (microstrip)
Figure 87
Figure 88
Nominal Trace Spacing from edge of one
differential pair to edge of another
differential pair
The greater of:
• 18 mils or 3x dielectric thickness (stripline)
• 20 mils or 3x dielectric thickness
(microstrip)
Figure 87
Figure 88
Trace Length L1, L1’– EP80579 Breakout
region and to AC CAP
Min = 0.75 in.
Max = 2.5 in.
Figure 94
Trace Length L2, L2’ – AC CAP to PCI
Express Device breakout region
Min = 4.0 in (stripline)
Min = 2.5 in (microstrip)
Max = 14.5 in. (stripline)
Max = 13.0 in. (microstrip)
Figure 94
Trace Length L3, L3’– Express Device
breakout region
Min = 0.75 in.
Max = 2.0 in.
Figure 94
Trace Length LT– EP80579 pin to PCI
Express Device
LT = L1 + L2 + L3 Figure 94
AC Blocking Capacitor–AC CAP 0.1 μF Figure 94
Length Tuning Requirements
Routing must remain on the same layer.
Maximum number of vias is 4.
LT-LT’ = ±5 mils
Figure 94
Figure 94. PCI Express Down Device Routing (EP80579 Transmit)
EP80579
PCI
Express*
Device
L1
L2
AC CAP
LT = L1 + L2 + L3
L3
L1'
L2'
AC CAP
L3'