Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line—PCI Express* Interface
Intel
®
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
151 Order Number: 320068-005US
• Containment of generated noise
Suppression is generally accomplished at the board level through component
placement, trace routing, etc. Containment is achieved at the system level through
inter-board connection, enclosure, etc. Non-linear distortion of the PCI Express signals
may increase the EMI and should be minimized. The spread spectrum clocking may be
used with the limitation in the modulation range (0 to -5000 ppm) and rate (30 -
33 KHz).
Many electromagnetic compatibility problems can be avoided by following EMI design
guidelines.
10.2.3 PCI Express (JTAG) Boundary Scan Pins
If boundary scan is not implemented on the system board, TMS and TDI must be
independently bused and pulled up, each with ~5 kΩ
resistors. TRST# and TCK must be
independently bused and pulled down, each with ~5 kΩ resistors. TDO must be left
open.
10.2.4 Terminating Unused PCI Express Ports
If the PCI Express port is not implemented on the system, leave the signals shown in
Table 57 as no connects.
If PCI Express ports will not be implemented on the platform, leave all PCI Express
transmit and receive signals disconnected. This includes the following signals:
• PEA0_Tn[7:0]
• PEA0_Tp[7:0]
• PEA0_Rn[7:0]
• PEA0_Rp[7:0]
10.2.5 Probing Differential Pairs
Be aware of limitations when probing the PCI Express Tx pairs on EP80579. There may
be a mismatch in impedance caused by the grid pitch and general routing in the
breakout region if the Tx probing is done close to the breakout region. In this case,
localized reflections may be misread as poor signal integrity. These reflections do not
propagate to the receive end of the transmission line, where most measurements
should be taken. Only Unit Interval width measurements should be taken on the
transmit side of the transmission line.
Table 57. No Connect Signals for Unused PCI Express Ports
PCI Express Port
PEA0_Tn[x]
PEA0_Tp[x]
PEA0_Rn[x]
PEA0_Rp[x]
Note: ‘x’ is the port number left unconnected.

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English