Intel
ยฎ
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 110
Platform System ClockโIntel
ยฎ
EP80579 Integrated Processor Product Line
8.3.5 IREF
The IREF pin on the CK410 is connected to ground through a 475 ฮฉ ยฑ1% resistor,
making the IREF 2.32 mA.
8.3.6 EMI Constraints
Clocks are a significant contributor to EMI. The following recommendations can aid in
EMI reduction:
โข Maintain uniform spacing between the two signals of each differential clock pair.
โข Route clocks on physical layer adjacent to the VSS reference plane only.
โข Use pull-down resistors to pull-down the unused clock signals to ground plane. This
prevents signals floating.
Figure 70. Decoupling Capacitors Placement and Connectivity
Decoupling
Caps
Decoupling
Caps
VDD_A
VDD_48