Intel EP80579

Intel
®
EP80579 Integrated Processor Product Line—System Memory Interface (SODIMM)
Intel
®
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
322 Order Number: 320068-005US
Figure A-2. Data/Mask/Strobe Signal Routing Topology Diagram
Table A-6. Data and Strobe Signal Group Routing Guidelines (Sheet 1 of 2)
Parameter
Routing Guidelines Figure
Data Byte Lane
Data & Data Mask Strobe
Signal Group Data & Mask (DQ & DM)
Byte Strobe (DQS/DQS#)
Topology Point-to-Point
Reference Plane Ground Referenced
Characteristic Trace Impedance
(Zo)
Single Ended Impedance:
40Ω ±10%
Layer assignment
• Layers 3/8
• Signals within the same Byte Lane must routed on
the same layer
Nominal Trace Width B= C = D = 6.5 mils Figure A-2
Trace-to-Trace spacing (e2e)
B = C = D = 3 x Trace
Width (min)
• Inter-pair Spacing:--
DQS/DQS# = 6 mils
(min)
• Pair-to-Pair Spacing:
20 mils (min)
Figure A-2
Clearance from other signals 20.0 mils (min)
SODIMM
EP80579
D
EP80579
Die
EP80579
Pin
Breakout
Routing
Breakin
Routing
Package
Trace
EP80579
Pad
Board
Routing
ABC
L
PKG
L
BREAKOUT
L
ROUTE
L
BREAKIN