Intel
ยฎ
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 126
System Memory Interface (DIMM)โIntel
ยฎ
EP80579 Integrated Processor Product Line
9.7.1.3 DDR2 Control Signals โ DDR_CS[1:0]#, DDR_ODT[1:0],
DDR_CKE[1:0]
In the EP80579 memory configuration, the DDR_CKE, DDR_ODT, and DDR_CS# signals
make up the control signal group. EP80579 provides six signals: DDR_CS[1:0]#,
DDR_ODT[1:0], and DDR_CKE[1:0] as control signals. In the EP80579 two DIMM
configuration, one chip select signal, one ODT control line, and one clock enable signal
are required for each rank. Figure 81 provides the inter-connect implementation of the
control signals to the DIMMs.
The EP80579 supports two single-rank and one dual-rank DIMMs. Always load the
DIMM slot farthest from EP80579 first (DIMM 0). DIMM 0 can be populated with either
a single-rank or a dual-rank DIMM. DIMM1 supports only a single-rank DIMM.
โข For single-rank DIMMs:
โ DIMM0[rank0] uses DDR_CS0#, DDR_ODT0, and DDR_CKE0
โ DIMM1[rank0] uses DDR_CS1#, DDR_ODT1, and DDR_CKE1
โข For dual-rank DIMMs (DIMM0 only):
โ DIMM0 [rank0] uses DDR_CS0#, DDR_ODT0, and DDR_CKE0
โ DIMM0 [rank1] uses DDR_CS1#, DDR_ODT1, and DDR_CKE1
โ DIMM1 should not be populated.
Table 42 and Figure 81 show the recommended topology and layout routing guidelines
for the Control signals in a two-DIMM configuration. For designs that use only one
DIMM, implement the topology for DIMM0 only, as shown in Figure 81, and eliminate
the DIMM-to-DIMM routing guidelines.
Table 43 and Table 44 provide EP80579 controller and DIMM ODT settings for write and
read operations to/from the DIMMs.
L
ROUTE
Max = 4.8 in
Length/Skew Matching Rules
โข The clock differential pairs need to match in
length within ยฑ 10 mils (CLK[x] = CLK[x]# ยฑ
10 mils, x=0.. 5)
โข Clock pairs should be matched in length to other
clock pairs within ยฑ 20 mils, regardless of DIMM
connection.
โข Clock signals should be matched in length to
CMD/ADD within ยฑ 20 mils. (CLK/CLK# = CMD/
ADD ยฑ 20 mils)
Table 41. Clock Signal Group Routing Guidelines (Sheet 2 of 2)
Parameter Routing Guidelines for 2-DIMM Solution Figure