Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 189
Low Pin Count (LPC) Interface—Intel
®
EP80579 Integrated Processor Product Line
14.2.3 Clock Signals -- CLK33
The 33 MHz clock is discussed in Section 8.2.3, “CLK33 Group” on page 99.
14.3 Trusted Platform Module (TPM) Guidelines
Trusted Platform Module(s) (TPM) are a Trusted Computing Platform Alliance* (TCPA)
low cost security solution to increase confidence on system security. The TPM is a
device that resides on the motherboard and is connected to EP80579 using the Low Pin
Count (LPC) bus to communicate with the rest of the board.
14.3.1 TPM Design Considerations
See the TPM Specification, Rev. 1.1 for TPM specific design considerations.
14.3.2 TPM Design Considerations
Routing requirements for the TPM LPC interface are as follows:
• LAD[3:0] (address/data lines) are shared with the Firmware Hub (FWH) component
and the Super I/O (SIO) device.
• LCLK (clock) must be connected to a 33 MHz clock (PCICLK).
• LRESET# (reset) must be connected to PLTRST#.
• LFRAME# (cycle termination) is shared with FWH and the SIO.
• SERIRQ (serialized IRQ) is shared with the SIO.
• LPCPD# (suspend status and LPC power down) is shared with SIO connected to
SUS_STAT#.
Figure 126 and Figure 127 are block diagrams showing the TPM interconnect to the
EP80579. Some of the LPC signals shown in the block diagram are shared with other
LPC components that reside on the LPC interconnect, such as the SIO and the FWH.
Table 70. Routing Recommendations
Parameter Routing Guideline
Signal Group All signals, except clock
Routing
Route over unbroken reference plane (Ground or Power)
microstrip or stripline
Minimum Trace Spacing (edge-
to-edge) with any other signals
4 times the reference plane height (which ever reference plane is closest.
For instance (only as an example):
• stripline: Reference plane at 4 mils on one side and 12 mils on other
side. Spacing needs to be 16 mils
• microstrip: Reference plane at 4 mils. Spacing needs to be 16 mils
Trace Length - applies to TL1,
TL2, TL3, and TL4 (Trace Length
from one device to other device)
1 inch min to 12 inch max (referred to total length restriction)
Total length of the traces from
Device1 to Device 5 (or last
device from the chain)
16.0” maximum (maximum distance between the end devices in the daisy
chain)
Vias 2 vias on each segment (TL1, TL2...)

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English