Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line—System Memory Interface (DIMM)
Intel
®
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
129 Order Number: 320068-005US
9.7.1.4 Address and Command Signals – DDR_MA[14:0],
DDR_BA[2:0], DDR_RAS#, DDR_CAS#, DDR_WE#
The address/command signals shown in Table 45 are source-clocked signals.
The address/command signals are source-clocked signals that include 15 system
memory address signals (MA[14:0]), 3 bank addresses (BA[2:0]), row address select
(RAS#), column address select (CAS#), and write enable (WE#). The address/
command signals are “clocked” into the DIMMs using the positive edge of the
differential clock signals. The EP80579 drives the address/command and clock signals
together.
Resistor packs are acceptable for the parallel (R
TT
) address/command termination
resistors, but address/command signals cannot be routed to the same resistor pack
(RPACK) used by data, data strobe, or control signals.
Figure 82 and Table 46 show the recommended topology and layout routing guidelines
for the DDR2-SDRAM address/command signals. Do not change layers. Place the
parallel termination resistors close to the DIMM. Use VTT termination for low power
requirement systems.
Table 44. Read Operation ODT Table
DIMM
Module
Read
Target
Controller
Configuration
DIMM 0
Configuration
DIMM 1
Configuration
DIMM 0 DIMM 1 Rank0 Rank1 Rank0 Rank1
SR Empty Rank0 120 Ω ODT Off n/a n/a n/a
DR Empty Rank0 120 Ω ODT Off 75 Ω n/a n/a
DR Empty Rank1 120 Ω 75 Ω ODT Off n/a n/a
SR SR Rank0 120 Ω ODT Off n/a 75 Ω n/a
SR SR Rank1 120 Ω 75 Ω n/a ODT Off n/a
Table 45. Address and Command Signals
Signal Description Signal Name
System Memory Address Signals DDR_MA[14:0]
Bank Addresses DDR_BA[2:0]
Row Address Select DDR_RAS#
Column Address Select DDR_CAS#
Write Enable DDR_WE#

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English