Intel
ยฎ
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 142
PCI Express* InterfaceโIntel
ยฎ
EP80579 Integrated Processor Product Line
10.1.8 Topology 2 โ EP80579 to PCI Express Connector
with Logic Analyzer Connector
Table 51 and Figure 92 summarize the layout routing solution space to a PCI Express
connector on the board with a logic analyzer connector. In this case, EP80579 is a
transmitter and the PCI Express connector is a receiver. All traces must be routed on
the same layer.
โข L1 starts from the EP80579 breakout region to the AC blocking capacitor via.
โข L2 is the main routing section that is from the AC blocking capacitor via to the logic
analyzer connector.
Table 50. PCI Express Connector Routing (EP80579 Receive)
Parameter Routing Guidelines Figure
Signal Group PEA0_Rn[7:0], PEA0_Rp[7:0]
Reference Plane Ground Referenced
Layer Assignment
Layers 3 or 8 (stripline)
Layers 1 or 10 (microstrip)
Characteristic Trace Impedance (Zo) 90 ฮฉ ยฑ10% (Differential)
Nominal Trace Width
4.5 mils (stripline)
4.75 mils (microstrip)
Figure 87
Figure 88
Nominal Trace Spacing within a pair from
edge to edge
5.5 mils (stripline)
5.25 mils (microstrip)
Figure 87
Figure 88
Nominal Trace Spacing from edge of one
differential pair to edge of another
differential pair
The greater of:
โข 18 mils or 3x dielectric thickness (stripline)
โข 20 mils or 5x dielectric thickness
(microstrip)
Figure 87
Figure 88
Trace Length L1, L1โโ EP80579 Breakout
region
Min = 0.5 in.
Max = 2.5 in.
Figure 91
Trace Length L2, L2โ โ PCI Express
connector
Min = 4.5 in.
Max = 15.5 in.(stripline)
Max = 15.0 in. (microstrip)
Figure 91
Trace Length LTโ EP80579 pin to PCI
Express connector
LT = L1 + L2 Figure 91
Length Tuning Requirements
Routing must remain on the same layer.
Maximum number of vias is 4.
LT-LTโ = ยฑ5 mils
Figure 91
Figure 91. PCI Express Connector Routing (EP80579 Receive)
EP80579
PCI
Express*
Connector
L1
L
2
LT = L1 + L2
L1'
L
2
'